JAJSFJ1 May 2018 DLPA4000
PRODUCTION DATA.
The DLPA4000 has power good indication for the DMD high-voltage (HV) regulator, DMD buck converters, DMD LDOs, and the LDO_DMD that supports the high-voltage regulator.
The DLPA4000 device continuously monitors the DMD HV regulator output rails DMD_RESET, DMD_VOFFSET and DMD_VBIAS. The DLP4000 device sets the DMD_ PG_FAULT bit in register 0x29 if either one of the output rails drops out of regulation. This situation can be due to a shorted output or an overload. The DMD_RESET threshold is 90%. The DMD_OFFSET and DMD_VBIAS thresholds are 86% (rising edge) and 66% (falling edge).
The power good signal for the two DMD buck converters indicate if each output voltage (PWR1_FB and PWR2_FB) maintains a specified range. The relative power good ratio is 72%, which indicates the level (output voltage falls below) at which the power good fault bit is asserted. The power good fault bits are in register 0x29, BUCK_DMD1_PG_FAULT and BUCK_DMD2_PG_FAULT.
The device monitors the output voltage of the DMD_LDO1 pin and the DMD_LDO2 pin. The power good fault of the LDO is asserted when the LDO voltage is below 80% (rising edge) or 60% (falling edge) of its intended value. The power good fault indication for the LDOs is in register 0x29, LDO_GP1_PG_FAULT, LDO_DMD1_PG_FAULT, LDO_GP2_PG_FAULT, LDO_DMD2_PG_FAULT.
The LDO_DMD pin regulates the DMD HV. The device asserts the power good fault of the LDO_DMD when the LDO voltage goes below 80% (rising edge) or 60% (falling edge) of its intended value. Register 0x29 stores the power good fault indication for this LDO as V5V5_LDO_DMD_PG_FAULT.