JAJSFJ1 May   2018 DLPA4000

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      システム・ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Parameters
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Description
    3. 8.3 Feature Description
      1. 8.3.1 Supply and Monitoring
        1. 8.3.1.1 Supply
        2. 8.3.1.2 Monitoring
          1. 8.3.1.2.1 Block Faults
          2. 8.3.1.2.2 Low Battery and UVLO
          3. 8.3.1.2.3 Thermal Protection
      2. 8.3.2 Illumination
        1. 8.3.2.1 Programmable Gain Block
        2. 8.3.2.2 LDO Illumination
        3. 8.3.2.3 Illumination Driver A
        4. 8.3.2.4 External MOSFETs
          1. 8.3.2.4.1 Gate series resistor (RG)
          2. 8.3.2.4.2 Gate series diode (DG)
          3. 8.3.2.4.3 Gate parallel capacitance (CG)
        5. 8.3.2.5 RGB Strobe Decoder
          1. 8.3.2.5.1 Break Before Make (BBM)
          2. 8.3.2.5.2 Openloop Voltage
          3. 8.3.2.5.3 Transient Current Limit
        6. 8.3.2.6 Illumination Monitoring
          1. 8.3.2.6.1 Power Good
          2. 8.3.2.6.2 RatioMetric Overvoltage Protection
      3. 8.3.3 External Power MOSFET Selection
        1. 8.3.3.1 Threshold Voltage
        2. 8.3.3.2 Gate Charge and Gate Timing
        3. 8.3.3.3 On-resistance RDS(on)
      4. 8.3.4 DMD Supplies
        1. 8.3.4.1 LDO DMD
        2. 8.3.4.2 DMD HV Regulator
        3. 8.3.4.3 DMD/DLPC Buck Converters
        4. 8.3.4.4 DMD Monitoring
          1. 8.3.4.4.1 Power Good
          2. 8.3.4.4.2 Overvoltage Fault
      5. 8.3.5 Buck Converters
        1. 8.3.5.1 LDO Bucks
        2. 8.3.5.2 General Purpose Buck Converters
        3. 8.3.5.3 Buck Converter Monitoring
          1. 8.3.5.3.1 Power Good
          2. 8.3.5.3.2 Overvoltage Fault
      6. 8.3.6 Auxiliary LDOs
      7. 8.3.7 Measurement System
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 SPI
      2. 8.5.2 Interrupt
      3. 8.5.3 Fast-Shutdown in Case of Fault
      4. 8.5.4 Protected Registers
      5. 8.5.5 Writing to EEPROM
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Component Selection for General-Purpose Buck Converters
    3. 9.3 System Example With DLPA4000 Internal Block Diagram
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up and Power-Down Timing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 LED Driver
        1. 11.1.1.1 PowerBlock Gate Control Isolation
        2. 11.1.1.2 VIN to PowerBlocks
        3. 11.1.1.3 Return Current from LEDs and RSense
        4. 11.1.1.4 RC Snubber
        5. 11.1.1.5 Capacitor Choice
      2. 11.1.2 General Purpose Buck 2
      3. 11.1.3 SPI Connections
      4. 11.1.4 RLIM Routing
      5. 11.1.5 LED Connection
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2 Detailed Design Procedure

To connect the 0.65 WXGA DMD (DLP650LE) or 0.65 1080p DMD (DLP650NE), DLPC4422 controller and DLPA4000, see the reference design schematic. When a circuit board layout is created from this schematic a very small circuit board is possible. An example small board layout is included in the reference design data base. Comply with the layout guidelines to achieve reliable projector operation. The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical OEM who specializes in designing optics for DLP projectors.

The component selection of the buck converter is mainly determined by the output voltage. Table 9 shows the recommended value for inductor LOUT and capacitor COUT for a given output voltage.

Table 9. Recommended Buck Converter LOUT and COUT

VOUT (V) LOUT (µH) COUT (µF)
MIN TYP MAX MIN MAX
1 - 1.5 1.5 2.2 4.7 22 68
1.5 - 3.3 2.2 3.3 4.7 22 68
3.3 - 5 3.3 4.7 22 68

Use Equation 11 to calculate the inductor peak-to-peak ripple current. Use Equation 12 the peak current. Use Equation 13to calculate teh RMS current. The inductor saturation current rating must be greater than the calculated peak current. The RMS or heating current rating of the inductor must be greater than the calculated RMS current.

Equation 11. DLPA4000 q_iloutripplepp_dlps132.gif

where

  • the switching frequency of the buck converter is approximately 600 kHz
Equation 12. DLPA4000 q_iloutpeak_dlps132.gif
Equation 13. DLPA4000 q_iloutrms_dlps132.gif

The capacitor value and ESR determines the level of output voltage ripple. Use ceramic or other low ESR capacitors. Recommended values range from 22 to 68 μF. Use Equation 14 to determine the required RMS current rating for the output capacitor.

Equation 14. DLPA4000 q_icoutrms_dlps132.gif

One other component for the buck converter configuration is needed. Use a charge pump capacitor between PWRx_SWITCH and PWRx_BOOST to drive the high-side MOSFET. The recommended value for the charge pump capacitor is 100 nF.

Because the switching edges of the buck converter are relatively fast, voltage overshoot and ringing can become a problem. To overcome this problem a snubber network is used. The snubber circuit consists of a resistor and capacitor that are connected in series from the switch node to ground. The snubber circuit is used to damp the parasitic inductances and capacitances during the switching transitions. This circuit reduces the ringing voltage and also reduces the number of ringing cycles. The snubber network is formed by RSNx and CSNx. More information on controlling switch-node ringing in synchronous buck converters and configuring the snubber can be found in Analog Applications Journal.