10.1 Power-Up and Power-Down Timing

The power-up and power-down sequence ensures a correct operation of the DLPA4000 and to prevent damage to the DMD. The DLPA4000 controls the correct sequencing of the DMD_VRESET, DMD_VBIAS, and DMD_VOFFSET to ensure a reliable operation of the DMD.

The general startup sequence of the supplies is described earlier in Supply and Monitoring. The power-up sequence of the high voltage DMD lines is especially important in order not to damage the DMD. A too large delta voltage between DMD_VBIAS and DMD_VOFFSET could cause the damage and should therefore be prevented.

After the device pulls PROJ_ON high, the DMD buck converters and LDOs energize (PWR1, PWR2, PWR3, PWR4) the DMD high voltage lines (HV) sequentially enable. At the end of this sequence, the DLPA4000 becomes fully powered and ready for projection.

1. DMD_VOFFSET
2. delay
3. VOFS_STATE_DURATION (register 0x10) DMD_VBIAS
4. delay
5. VBIAS_STATE_DURATION (register 0x11) DMD_VRESET

For shutdown there are two sequences, normal shutdown (Figure 23) and a fault fast shutdown used in case a fault occurs (Figure 24).

This is the shutdown sequence during normal mode operation

1. 25-ms delay
2. PROJ_ON pin goes low
3. DMD_VBIAS and DMD_VRESET stop regulating
4. 10 ms delay
5. DMD_OFFSET stops regulating
6. RESET_Z goes low
7. 1 ms delay
8. all three voltages discharge
9. all other supplies de-energized
10. INT_Z remains high

INT_Z remains high during the shutdown sequence because no fault occurred. During the power-down sequence the device makes sure the HV levels do not violate the DMD specifications on these three lines. For this it is important to select the capacitors such that C_VOFFSET is equal to C_VRESET and C_VBIAS is ≤ C_VOFFSET, C_VBIAS.

The fast shutdown mode (Figure 24) sequence starts in case a fault occurs (INT_Z is pulled low), for instance due to overheating.

Use register 0x01 to enable and disable fast shutdown mode (FAST_SHUTDOWN_EN). Fast shutdown mode is the default mode. After the fault occurs, regulation of DMD_VBIAS and DMD_VRESET is stopped. The time (delay) between fault and stop of regulation can be controlled via register 0x0F (VBIAS/VRST_DELAY). The delay can be selected between 4 µs and approximately 1.1 ms, where the default is approximately 540 µs. A defined delay-time after the regulation stopped, all three high voltages lines are discharged and RESET_Z is pulled low. The delay can be controlled via register 0x0F (VOFS/VRESETZ_DELAY). Delay can be selected between 4 µs and approximately1.1ms. The default is ~4 µs. Finally the internal DMD_EN signal is pulled low.

The DLPA4000 device remains in standby state until the fault resolves. The device restarts then the fault resolves. The restart sequence begins when the device energizes the PWR_3 pin and follows the same steps as the regular startup sequence (see Figure 24). select capacitors so that C_VOFFSET is equal to C_VRESET and C_VBIAS is ≤ C_VOFFSET, C_VBIAS. This selection criteria ensures proper discharge timing and discharge levels.

NOTE:

Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under SPI control.

Figure 23. Power Sequence Normal Shutdown Mode

NOTE:

Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under SPI control.

Figure 24. Power Sequence Fault Fast Shutdown Mode