JAJSFO9I December   2015  – August 2024 DLPC230-Q1 , DLPC231-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics for Fixed Voltage I/O
    7. 5.7  DMD High-Speed SubLVDS Electrical Characteristics
    8. 5.8  DMD Low-Speed SubLVDS Electrical Characteristics
    9. 5.9  OpenLDI LVDS Electrical Characteristics
    10. 5.10 Power Dissipation Characterisics
    11. 5.11 System Oscillators Timing Requirements
    12. 5.12 Power Supply and Reset Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 OpenLDI Interface General Timing Requirements
    15. 5.15 Parallel/OpenLDI Interface Frame Timing Requirements
    16. 5.16 Host/Diagnostic Port SPI Interface Timing Requirements
    17. 5.17 Host/Diagnostic Port I2C Interface Timing Requirements
    18. 5.18 Flash Interface Timing Requirements
    19. 5.19 TPS99000-Q1 SPI Interface Timing Requirements
    20. 5.20 TPS99000-Q1 AD3 Interface Timing Requirements
    21. 5.21 DLPC23x-Q1 I2C Port Interface Timing Requirements
    22. 5.22 Chipset Component Usage Specification
  7. 6 Parameter Measurement Information
    1. 6.1 HOST_IRQ Usage Model
    2. 6.2 Input Source
      1. 6.2.1 Supported Input Sources
      2. 6.2.2 Parallel Interface Supported Data Transfer Formats
        1. 6.2.2.1 OpenLDI Interface Supported Data Transfer Formats
          1. 6.2.2.1.1 OpenLDI Interface Bit Mapping Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Parallel Interface
      2. 7.3.2  OpenLDI Interface
      3. 7.3.3  DMD (SubLVDS) Interface
      4. 7.3.4  Serial Flash Interface
      5. 7.3.5  Serial Flash Programming
      6. 7.3.6  Host Command and Diagnostic Processor Interfaces
      7. 7.3.7  GPIO Supported Functionality
      8. 7.3.8  Built-In Self Test (BIST)
      9. 7.3.9  EEPROMs
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Debug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Display Mode
      3. 7.4.3 Calibration Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Head-Up Display
        1. 8.2.1.1 Design Requirements
      2. 8.2.2 Headlight
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Headlight Video Input
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Management
      2. 8.3.2 Hot Plug Usage
      3. 8.3.3 Power Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
        2. 8.4.1.2  DLPC23x-Q1 Reference Clock
          1. 8.4.1.2.1 Recommended Crystal Oscillator Configuration
        3. 8.4.1.3  DMD Interface Layout Considerations
        4. 8.4.1.4  General PCB Recommendations
        5. 8.4.1.5  General Handling Guidelines for Unused CMOS-Type Pins
        6. 8.4.1.6  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
        7. 8.4.1.7  Number of Layer Changes
        8. 8.4.1.8  Stubs
        9. 8.4.1.9  Terminations
        10. 8.4.1.10 Routing Vias
        11. 8.4.1.11 Layout Examples
      2. 8.4.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Device Markings DLPC230-Q1 or DLPC230S-Q1
        2. 9.1.2.2 Device Markings DLPC231-Q1 or DLPC231S-Q1
        3. 9.1.2.3 Video Timing Parameter Definitions
    2. 9.2 Trademarks
    3. 9.3 静電気放電に関する注意事項
    4. 9.4 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.8 DMD Low-Speed SubLVDS Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VCM Steady-state common mode voltage 1.8V SubLVDS (I/O type 4,5) 0.8 0.9 1.0 V
VCM (Δpp)(1) VCM change peak-to-peak (during switching) 1.8V SubLVDS (I/O type 4,5) 75 mV
VCM (Δss)(1) VCM change steady state 1.8V SubLVDS (I/O type 4,5) –10 10 mV
|VOD|(2) Differential output voltage magnitude. RBGR = 75kΩ. 1.8V SubLVDS (I/O type 4,5) 155 200 250 mV
VOD (Δ)(3) VOD change (between logic states) 1.8V SubLVDS (I/O type 4,5) –10 10 mV
VOH Single-ended output voltage high 1.8V SubLVDS (I/O type 4,5) 0.88 1.00 1.125 V
VOL Single-ended output voltage low 1.8V SubLVDS (I/O type 4,5) 0.675 0.80 0.925 V
tR(2) Differential output rise time 1.8V SubLVDS (I/O type 4,5) 250 ps
tF(2) Differential output fall time 1.8V SubLVDS (I/O type 4,5) 250 ps
tMAX Max switching rate 1.8V SubLVDS (I/O type 4,5) 240 Mbps
DCout Output duty cycle 1.8V SubLVDS (I/O type 4,5) 45% 50% 55%
Txterm Internal differential termination 1.8V SubLVDS (I/O type 4,5) 80 100 120 Ω
(1) Definition of VCM changes:
DLPC230-Q1 DLPC231-Q1
(2) Note that VOD is the differential voltage swing measured across a 100Ω termination resistance connected directly between the transmitter differential pins. |VOD| is the magnitude of the peak to peak voltage swing across the P and N output pins. Because VCM cancels out when measured differentially, VOD voltage swings relative to 0. Rise and fall times are defined for the differential VOD signal as follows:

DLPC230-Q1 DLPC231-Q1

(3) When TX data input = '1', differential output voltage VOD1 is defined. When TX data input = '0', differential output voltage VOD0 is defined. As such, the steady state magnitude of the difference is: |VOD| (Δ) = ||VOD1| – |VOD0||.