JAJSFO9I December   2015  – August 2024 DLPC230-Q1 , DLPC231-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics for Fixed Voltage I/O
    7. 5.7  DMD High-Speed SubLVDS Electrical Characteristics
    8. 5.8  DMD Low-Speed SubLVDS Electrical Characteristics
    9. 5.9  OpenLDI LVDS Electrical Characteristics
    10. 5.10 Power Dissipation Characterisics
    11. 5.11 System Oscillators Timing Requirements
    12. 5.12 Power Supply and Reset Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 OpenLDI Interface General Timing Requirements
    15. 5.15 Parallel/OpenLDI Interface Frame Timing Requirements
    16. 5.16 Host/Diagnostic Port SPI Interface Timing Requirements
    17. 5.17 Host/Diagnostic Port I2C Interface Timing Requirements
    18. 5.18 Flash Interface Timing Requirements
    19. 5.19 TPS99000-Q1 SPI Interface Timing Requirements
    20. 5.20 TPS99000-Q1 AD3 Interface Timing Requirements
    21. 5.21 DLPC23x-Q1 I2C Port Interface Timing Requirements
    22. 5.22 Chipset Component Usage Specification
  7. 6 Parameter Measurement Information
    1. 6.1 HOST_IRQ Usage Model
    2. 6.2 Input Source
      1. 6.2.1 Supported Input Sources
      2. 6.2.2 Parallel Interface Supported Data Transfer Formats
        1. 6.2.2.1 OpenLDI Interface Supported Data Transfer Formats
          1. 6.2.2.1.1 OpenLDI Interface Bit Mapping Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Parallel Interface
      2. 7.3.2  OpenLDI Interface
      3. 7.3.3  DMD (SubLVDS) Interface
      4. 7.3.4  Serial Flash Interface
      5. 7.3.5  Serial Flash Programming
      6. 7.3.6  Host Command and Diagnostic Processor Interfaces
      7. 7.3.7  GPIO Supported Functionality
      8. 7.3.8  Built-In Self Test (BIST)
      9. 7.3.9  EEPROMs
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Debug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Display Mode
      3. 7.4.3 Calibration Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Head-Up Display
        1. 8.2.1.1 Design Requirements
      2. 8.2.2 Headlight
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Headlight Video Input
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Management
      2. 8.3.2 Hot Plug Usage
      3. 8.3.3 Power Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
        2. 8.4.1.2  DLPC23x-Q1 Reference Clock
          1. 8.4.1.2.1 Recommended Crystal Oscillator Configuration
        3. 8.4.1.3  DMD Interface Layout Considerations
        4. 8.4.1.4  General PCB Recommendations
        5. 8.4.1.5  General Handling Guidelines for Unused CMOS-Type Pins
        6. 8.4.1.6  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
        7. 8.4.1.7  Number of Layer Changes
        8. 8.4.1.8  Stubs
        9. 8.4.1.9  Terminations
        10. 8.4.1.10 Routing Vias
        11. 8.4.1.11 Layout Examples
      2. 8.4.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Device Markings DLPC230-Q1 or DLPC230S-Q1
        2. 9.1.2.2 Device Markings DLPC231-Q1 or DLPC231S-Q1
        3. 9.1.2.3 Video Timing Parameter Definitions
    2. 9.2 Trademarks
    3. 9.3 静電気放電に関する注意事項
    4. 9.4 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.14 OpenLDI Interface General Timing Requirements

The DLPC23x-Q1 ASIC input interface supports a subset of the industry standard OpenLDI (FPD-Link I) interface (Open LVDS Display Interface Specification v0.95 - May 13, 1999). Specifically, from the standard, the ASIC supports the 24-bit, Single Pixel Format, using the Unbalanced Operating Mode and Pixel Mapping.
MIN NOM MAX UNIT
ƒclock Clock frequency, L1_CLK_P/N, L2_CLK_P/N 20.0 110 MHz
tp Clock period, PCLK 50% reference points 9.091 50 ns
tskew Skew Margin (between clock and data ) ƒclock = 85 MHz –400 (5) 0 400(5) ps
tskew_ports Clock to clock skew margin between ports on same ASIC, and between ports on different ASICs 1 clocks
tip0 Input data position 1 (tp / 7) – tskew (tp / 7) (tp / 7) + tskew ps
tip6 Input data position 2 2 * (tp / 7) – tskew 2 * (tp / 7) 2 * (tp / 7) + tskew ps
tip5 Input data position 3 3 * (tp / 7) – tskew 3 * (tp / 7) 3 * (tp / 7) + tskew ps
tip4 Input data position 4 4 * (tp / 7) – tskew 4 * (tp / 7) 4 * (tp / 7) + tskew ps
tip3 Input data position 5 5 * (tp / 7) – tskew 5 * (tp / 7) 5 * (tp / 7) + tskew ps
tip2 Input data position 6 6 * (tp / 7) – tskew 6 * (tp / 7) 6 * (tp / 7) + tskew ps
tjitter Input Jitter Tolerance
(cycle to cycle, peak to peak)		 100 ps
ƒspread Supported Spread Spectrum range percent of ƒclock rate –1%(1) +1%(2)
ƒmod Supported Spread Spectrum Modulation Frequency(3)(4) 25 65 kHz
(1) This value is limited by the minimum clock frequency for ƒclock (that is, if ƒclock = min clock freq, then ƒspread max = 0%).
(2) This value is limited by the maximum clock frequency for ƒclock (that is, if ƒclock = max clock freq, then ƒspread max = 0%).
(3) Modulation Waveforms supported: Sine and Triangle.
(4) Spread spectrum on OpenLDI interfaces was simulated, but not tested.
(5) t skew for other ƒclock values can be estimated by +/- tskew = -7.143 × ƒclock + 1007.1 - (tjitter - 100)
DLPC230-Q1 DLPC231-Q1 OpenLDI Interface Timing Figure 5-4 OpenLDI Interface Timing