JAJSFO9I December   2015  – August 2024 DLPC230-Q1 , DLPC231-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics for Fixed Voltage I/O
    7. 5.7  DMD High-Speed SubLVDS Electrical Characteristics
    8. 5.8  DMD Low-Speed SubLVDS Electrical Characteristics
    9. 5.9  OpenLDI LVDS Electrical Characteristics
    10. 5.10 Power Dissipation Characterisics
    11. 5.11 System Oscillators Timing Requirements
    12. 5.12 Power Supply and Reset Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 OpenLDI Interface General Timing Requirements
    15. 5.15 Parallel/OpenLDI Interface Frame Timing Requirements
    16. 5.16 Host/Diagnostic Port SPI Interface Timing Requirements
    17. 5.17 Host/Diagnostic Port I2C Interface Timing Requirements
    18. 5.18 Flash Interface Timing Requirements
    19. 5.19 TPS99000-Q1 SPI Interface Timing Requirements
    20. 5.20 TPS99000-Q1 AD3 Interface Timing Requirements
    21. 5.21 DLPC23x-Q1 I2C Port Interface Timing Requirements
    22. 5.22 Chipset Component Usage Specification
  7. 6 Parameter Measurement Information
    1. 6.1 HOST_IRQ Usage Model
    2. 6.2 Input Source
      1. 6.2.1 Supported Input Sources
      2. 6.2.2 Parallel Interface Supported Data Transfer Formats
        1. 6.2.2.1 OpenLDI Interface Supported Data Transfer Formats
          1. 6.2.2.1.1 OpenLDI Interface Bit Mapping Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Parallel Interface
      2. 7.3.2  OpenLDI Interface
      3. 7.3.3  DMD (SubLVDS) Interface
      4. 7.3.4  Serial Flash Interface
      5. 7.3.5  Serial Flash Programming
      6. 7.3.6  Host Command and Diagnostic Processor Interfaces
      7. 7.3.7  GPIO Supported Functionality
      8. 7.3.8  Built-In Self Test (BIST)
      9. 7.3.9  EEPROMs
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Debug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Display Mode
      3. 7.4.3 Calibration Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Head-Up Display
        1. 8.2.1.1 Design Requirements
      2. 8.2.2 Headlight
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Headlight Video Input
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Management
      2. 8.3.2 Hot Plug Usage
      3. 8.3.3 Power Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
        2. 8.4.1.2  DLPC23x-Q1 Reference Clock
          1. 8.4.1.2.1 Recommended Crystal Oscillator Configuration
        3. 8.4.1.3  DMD Interface Layout Considerations
        4. 8.4.1.4  General PCB Recommendations
        5. 8.4.1.5  General Handling Guidelines for Unused CMOS-Type Pins
        6. 8.4.1.6  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
        7. 8.4.1.7  Number of Layer Changes
        8. 8.4.1.8  Stubs
        9. 8.4.1.9  Terminations
        10. 8.4.1.10 Routing Vias
        11. 8.4.1.11 Layout Examples
      2. 8.4.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Device Markings DLPC230-Q1 or DLPC230S-Q1
        2. 9.1.2.2 Device Markings DLPC231-Q1 or DLPC231S-Q1
        3. 9.1.2.3 Video Timing Parameter Definitions
    2. 9.2 Trademarks
    3. 9.3 静電気放電に関する注意事項
    4. 9.4 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.1 Design Requirements

The DLPC23x-Q1 is a controller for the DMD and the timing of the RGB LEDs in the HUD. It requests the proper timing and amplitude from the LEDs to achieve the requested color and brightness from the HUD across the entire operating range. It synchronizes the DMD with these LEDs to display full-color video content sent by the host.

The DLPC23x-Q1 receives command and input video data from a host processor in the vehicle. Read and write (R/W) commands can be sent using either the I2C bus or SPI bus. The bus that is not being used for R/W commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an OpenLDI bus or a parallel 24-bit bus. The SPI flash memory provides the embedded software for the DLPC23x-Q1’s embedded processor, color calibration data, and default settings. The TPS99000-Q1 provides diagnostic and monitoring information to the DLPC23x-Q1 using an SPI bus and several other control signals such as PARKZ, INTZ, and RESETZ to manage power-up and power-down sequencing. The DLPC23x-Q1 interfaces to a TMP411 through I2C for temperature information.

The outputs of the DLPC23x-Q1 are LED drive information to the TPS99000-Q1, control signals to the DMD, and monitoring and diagnostics information to the host processor. Based on a host requested brightness and the operating temperature, the DLPC23x-Q1 determines the proper timing and amplitudes for the LEDs. It passes this information to the TPS99000-Q1 using an SPI bus and several additional control signals such as D_EN, S_EN, and SEQ_STRT. It controls the DMD mirrors by sending data over a SubLVDS bus. It can alert the host about any critical errors using a HOST_IRQ signal.

The TPS99000-Q1 is a highly-integrated mixed-signal IC that controls DMD power, the analog response of the LEDs, and provides monitoring and diagnostics information for the HUD system. The power sequencing and monitoring blocks of the TPS99000-Q1 properly power up the DMD, provide accurate DMD voltage rails, as well as monitor the system’s power rails during operation. The integration of these functions into one IC significantly reduces design time and complexity. The highly accurate photodiode (PD) measurement system and the dimming controller block precisely control the LED response. This enables a DLP technology HUD to achieve a very high dimming range (> 5000:1) with accurate brightness and color across the temperature range of the system. Finally, the TPS99000-Q1 has several general-purpose ADCs that developers can use for system-level monitoring, such as over-brightness detection.

The TPS99000-Q1 receives inputs from the DLPC23x-Q1, power rail voltages for monitoring, a photodiode that is used to measure LED response, the host processor, and potentially several other ADC ports. The DLPC23x-Q1 sends commands to the TPS99000-Q1 over an SPI port and several other control signals. The TPS99000-Q1 includes watchdogs to monitor the DLPC23x-Q1 and verify it is operating as expected. The power rails are monitored by the TPS99000-Q1 to detect power failures or glitches and request a proper power down of the DMD in case of an error. The photodiode’s current is measured and amplified using a transimpedance amplifier (TIA) within the TPS99000-Q1. The host processor can read diagnostics information from the TPS99000-Q1 using a dedicated SPI bus, adding an independent monitoring path from the host processor. Additionally the host can request the system to be turned on or off using a PROJ_ON signal. The TPS99000-Q1 has several general-purpose ADCs that can be used to implement other system features such as over-brightness and over-temperature detection.

The outputs of the TPS99000-Q1 are LED drive signals, diagnostic information, and error alerts to the DLPC23x-Q1. The TPS99000-Q1 has signals connected to the LM3409 buck controller for high power LEDs and to discrete hardware that control the LEDs. The TPS99000-Q1 can output diagnostic information to the host and the DLPC23x-Q1 over two SPI buses. It also has signals such as RESETZ, PARKZ, and INTZ that can be used to trigger power down or reset sequences.

The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video data) and produces a mechanical output (mirror position). The electrical interface to the DMD is a SubLVDS interface driven with the DLPC23x-Q1. The mechanical output is the state of more than 1.3 million mirrors in the DMD array that can be tilted ±12°. In a projection system, the mirrors are used as pixels to display an image.