JAJSFO9I December   2015  – August 2024 DLPC230-Q1 , DLPC231-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics for Fixed Voltage I/O
    7. 5.7  DMD High-Speed SubLVDS Electrical Characteristics
    8. 5.8  DMD Low-Speed SubLVDS Electrical Characteristics
    9. 5.9  OpenLDI LVDS Electrical Characteristics
    10. 5.10 Power Dissipation Characterisics
    11. 5.11 System Oscillators Timing Requirements
    12. 5.12 Power Supply and Reset Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 OpenLDI Interface General Timing Requirements
    15. 5.15 Parallel/OpenLDI Interface Frame Timing Requirements
    16. 5.16 Host/Diagnostic Port SPI Interface Timing Requirements
    17. 5.17 Host/Diagnostic Port I2C Interface Timing Requirements
    18. 5.18 Flash Interface Timing Requirements
    19. 5.19 TPS99000-Q1 SPI Interface Timing Requirements
    20. 5.20 TPS99000-Q1 AD3 Interface Timing Requirements
    21. 5.21 DLPC23x-Q1 I2C Port Interface Timing Requirements
    22. 5.22 Chipset Component Usage Specification
  7. 6 Parameter Measurement Information
    1. 6.1 HOST_IRQ Usage Model
    2. 6.2 Input Source
      1. 6.2.1 Supported Input Sources
      2. 6.2.2 Parallel Interface Supported Data Transfer Formats
        1. 6.2.2.1 OpenLDI Interface Supported Data Transfer Formats
          1. 6.2.2.1.1 OpenLDI Interface Bit Mapping Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Parallel Interface
      2. 7.3.2  OpenLDI Interface
      3. 7.3.3  DMD (SubLVDS) Interface
      4. 7.3.4  Serial Flash Interface
      5. 7.3.5  Serial Flash Programming
      6. 7.3.6  Host Command and Diagnostic Processor Interfaces
      7. 7.3.7  GPIO Supported Functionality
      8. 7.3.8  Built-In Self Test (BIST)
      9. 7.3.9  EEPROMs
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Debug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Display Mode
      3. 7.4.3 Calibration Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Head-Up Display
        1. 8.2.1.1 Design Requirements
      2. 8.2.2 Headlight
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Headlight Video Input
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Management
      2. 8.3.2 Hot Plug Usage
      3. 8.3.3 Power Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
        2. 8.4.1.2  DLPC23x-Q1 Reference Clock
          1. 8.4.1.2.1 Recommended Crystal Oscillator Configuration
        3. 8.4.1.3  DMD Interface Layout Considerations
        4. 8.4.1.4  General PCB Recommendations
        5. 8.4.1.5  General Handling Guidelines for Unused CMOS-Type Pins
        6. 8.4.1.6  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
        7. 8.4.1.7  Number of Layer Changes
        8. 8.4.1.8  Stubs
        9. 8.4.1.9  Terminations
        10. 8.4.1.10 Routing Vias
        11. 8.4.1.11 Layout Examples
      2. 8.4.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Device Markings DLPC230-Q1 or DLPC230S-Q1
        2. 9.1.2.2 Device Markings DLPC231-Q1 or DLPC231S-Q1
        3. 9.1.2.3 Video Timing Parameter Definitions
    2. 9.2 Trademarks
    3. 9.3 静電気放電に関する注意事項
    4. 9.4 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1.6 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths

Table 8-5 Max Pin-to-Pin PCB Interconnect Recommendations—DMD
ASIC INTERFACE SIGNAL INTERCONNECT TOPOLOGY(1)(2) UNIT
DMD SINGLE BOARD SIGNAL ROUTING LENGTH MULTI-BOARD SIGNAL ROUTING LENGTH
DMD_HS0_CLK_P
DMD_HS0_CLK_N		 6.0
(152.4)		 See (3) in
(mm)
DMD_HS0_WDATA0_P
DMD_HS0_WDATA0_N		 6.0
(152.4)		 See (3) in
(mm)
DMD_HS0_WDATA1_P
DMD_HS0_WDATA1_N
DMD_HS0_WDATA2_P
DMD_HS0_WDATA2_N
DMD_HS0_WDATA3_P
DMD_HS0_WDATA3_N
DMD_HS0_WDATA4_P
DMD_HS0_WDATA4_N
DMD_HS0_WDATA5_P
DMD_HS0_WDATA5_N
DMD_HS0_WDATA6_P
DMD_HS0_WDATA6_N
DMD_HS0_WDATA7_P
DMD_HS0_WDATA7_N
DMD_HS1_CLK_P
DMD_HS1_CLK_N		 6.0
(152.4)		 See (3) in
(mm)
DMD_HS1_WDATA0_P
DMD_HS1_WDATA0_N		 6.0
(152.4)		 See (3) in
(mm)
DMD_HS1_WDATA1_P
DMD_HS1_WDATA1_N
DMD_HS1_WDATA2_P
DMD_HS1_WDATA2_N
DMD_HS1_WDATA3_P
DMD_HS1_WDATA3_N
DMD_HS1_WDATA4_P
DMD_HS1_WDATA4_N
DMD_HS1_WDATA5_P
DMD_HS1_WDATA5_N
DMD_HS1_WDATA6_P
DMD_HS1_WDATA6_N
DMD_HS1_WDATA7_P
DMD_HS1_WDATA7_N
DMD_LS0_CLK_P
DMD_LS0_CLK_N		 6.5
(165.1)		 See (3) in
(mm)
DMD_LS0_WDATA_P
DMD_LS0_WDATA_N		 6.5
(165.1)		 See (3) in
(mm)
DMD_LS0_RDATA 6.5
(165.1)		 See (3) in
(mm)
DMD_LS1_RDATA 6.5
(165.1)		 See (3) in
(mm)
DMD_DEN_ARSTZ N/A N/A in
(mm)
(1) Max signal routing length includes escape routing.
(2) Multi-board DMD routing length is more restricted due to the impact of the connector.
(3) Due to board variations, these are impossible to define. Any board designs must SPICE simulate with the ASIC IBIS models to verify signal routing lengths do not exceed requirements.
Table 8-6 Max Pin-to-Pin PCB Interconnect Recommendations - TPS99000-Q1
ASIC INTERFACE SIGNAL INTERCONNECT TOPOLOGY (1)(2) UNIT
TPS99000-Q1 SINGLE BOARD SIGNAL ROUTING LENGTH MULTI-BOARD SIGNAL ROUTING LENGTH
PMIC_LEDSEL(3) 6.0
(152.4)		 See (3) in
(mm)
PMIC_LEDSEL(2)
PMIC_LEDSEL(1)
PMIC_LEDSEL(0)
PMIC_ADC3_CLK
PMIC_ADC3_MOSI
PMIC_ADC3_MISO
PMIC_SEQ_STRT
(1) Max signal routing length includes escape routing.
(2) Multiboard DMD routing length is more restricted due to the impact of the connector.
(3) Due to board variations, these are impossible to define. Any board designs must SPICE simulate with the ASIC IBIS models to verify signal routing lengths do not exceed requirements.
Table 8-7 High-Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING (1)(2)
INTERFACE SIGNAL GROUP REFERENCE SIGNAL MAX MISMATCH

ZDQ324

MAX MISMATCH ZEK324

 UNIT
DMD(3) DMD_HS0_WDATA0_P
DMD_HS0_WDATA0_N		 DMD_HS0_CLK_P
DMD_HS0_CLK_N		 ±1.0
(±25.4)		 ±1.0
(±25.4)		 in
(mm)
DMD_HS0_WDATA1_P
DMD_HS0_WDATA1_N
DMD_HS0_WDATA2_P
DMD_HS0_WDATA2_N
DMD_HS0_WDATA3_P
DMD_HS0_WDATA3_N
DMD_HS0_WDATA4_P
DMD_HS0_WDATA4_N
DMD_HS0_WDATA5_P
DMD_HS0_WDATA5_N
DMD_HS0_WDATA6_P
DMD_HS0_WDATA6_N
DMD_HS0_WDATA7_P
DMD_HS0_WDATA7_N
DMD(4) DMD_HS0_x_P DMD_HS0_x_N ±0.025
(±0.635)		 0.0315±0.025
(0.8±0.635)		 in
(mm)
DMD(3) DMD_HS1_WDATA0_P
DMD_HS1_WDATA0_N		 DMD_HS1_CLK_P
DMD_HS1_CLK_N		 ±1.0
(±25.4)		 ±1.0
(±25.4)		 in
(mm)
DMD_HS1_WDATA1_P
DMD_HS1_WDATA1_N
DMD_HS1_WDATA2_P
DMD_HS1_WDATA2_N
DMD_HS1_WDATA3_P
DMD_HS1_WDATA3_N
DMD_HS1_WDATA4_P
DMD_HS1_WDATA4_N
DMD_HS1_WDATA5_P
DMD_HS1_WDATA5_N
DMD_HS1_WDATA6_P
DMD_HS1_WDATA6_N
DMD_HS1_WDATA7_P
DMD_HS1_WDATA7_N
DMD(4) DMD_HS1_x_P DMD_HS1_x_N ±0.025
(±0.635)		 0.0315±0.025
(0.8±0.635) (5)		 in
(mm)
DMD(3) DMD_LS0_WDATA_P
DMD_LS0_WDATA_N		 DMD_LS0_CLK_P
DMD_LS0_CLK_N		 ±1.0
(±25.4)		 ±1.0
(±25.4)		 in
(mm)
DMD DMD_LS0_WDATA
DMD_LS0_RDATA
DMD_LS1_RDATA		 DMD_LS0_CLK ±0.2
(±5.08)		 ±0.2
(±5.08)		 in
(mm)
DMD(4) DMD_LS0_x_P DMD_LS0_x_N ±0.025
(±0.635)		 0.0315±0.025
(0.8±0.635) (5)		 in
(mm)
DMD DMD_DEN_ARSTZ N/A N/A N/A in
(mm)
TPS99000-Q1 PMIC_LEDSEL(3) PMIC_ADC3_CLK ±1.0
(±25.4)		 ±1.0
(±25.4)		 in
(mm)
PMIC_LEDSEL(2)
PMIC_LEDSEL(1)
PMIC_LEDSEL(0)
PMIC_SEQ_STRT
PMIC_ADC3_MOSI
OpenLDI Lx_DATAx_N Lx_DATAx_P

N/A

 0.0315±0.025
(0.8±0.635) (6)		 in
(mm)
OpenLDI Lx_CLK_N Lx_CLK_P

N/A

 0.0315±0.025
(0.8±0.635) (6)		 in
(mm)
(1) These routing requirements are specific to the PCB routing. Internal package routing mismatches in the DLPC23x-Q1 and DMD have already been accounted for in these requirements.
(2) Training is applied to DMD HS data lines, so defined matching requirements are slightly relaxed.
(3) This is an inter-pair specification (that is, differential pair to differential pair within the group).
(4) This is an intra-pair specification (that is, length mismatch between P and N for the same pair).
(5) ZEK324 package trace length of the DMD interface differential N signals are 0.8mm longer than the P signals to simplify matching of the PCB signals.
(6) ZEK324 package trace length of the OpenLDI interface differential P signals are 0.8mm longer than the N signals to simplify matching of the PCB signals.