JAJSFU7E December   2013  – March 2019 DLPC2607

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Typical Current and Power Dissipation
    6. 6.6  I/O Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  Parallel I/F Frame Timing Requirements
    9. 6.9  Parallel I/F General Timing Requirements
    10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
    11. 6.11 BT.656 I/F General Timing Requirements
    12. 6.12 100- to 120-Hz Operational Limitations
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 mDDR Memory Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
    4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Reference Clock
        2. 8.2.2.2 mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Hot-Plug Usage
        2. 8.2.3.2 Maximum Signal Transition Time
        3. 8.2.3.3 Configuration Control
        4. 8.2.3.4 White Point Correction Light Sensor
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 System Power I/O State Considerations
    4. 9.4 Power-Up Initialization Sequence
    5. 9.5 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  Internal ASIC PLL Power
      2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
      3. 10.1.3  SPI Signal Routing
      4. 10.1.4  mDDR Memory and DMD Interface Considerations
      5. 10.1.5  PCB Design
      6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
      7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
      8. 10.1.8  I/F Specific PCB Routing
      9. 10.1.9  Number of Layer Changes
      10. 10.1.10 Stubs
      11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 デバイスの項目表記
        1. 11.1.2.1 デバイス・マーキング
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 付録: パッケージ･オプション
      1. 12.1.1 パッケージ情報

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZVB|176
サーマルパッド・メカニカル・データ

6.14 DMD Interface Timing Requirements

The DLPC2607 ASIC DMD interface consists of a 76.19-MHz (nominal) DDR output-only interface with LVCMOS signaling. (see (5))
MIN MAX UNIT
ƒclock Clock frequency, DMD_DCLK and DMD_SAC_CLK(1) 76.175 76.206 MHz
tp_clkper Clock period, DMD_DCLK and DMD_SAC_CLK 50% reference points 13.122 13.128 ns
tp_wh Pulse duration low, DMD_DCLK and DMD_SAC_CLK 50% reference points 6.2 ns
tp_wl Pulse duration high, DMD_DCLK and DMD_SAC_CLK 50% reference points 6.2 ns
tt Transition time – all signals 20% to 80% reference points 0.3 2 ns
tp_su Output setup time – DMD_D(14:0),
DMD_SCTRL, DMD_LOADB and DMD_TRC
relative to both rising and falling edges of DMD_DCLK(2)(4) 		50% reference points 1.5 ns
tp_h Output hold time – DMD_D(14:0),
DMD_SCTRL,DMD_LOADB and DMD_TRC
signals relative to both rising and falling edges of DMD_DCLK(2)(4) 		50% reference points 1.5 ns
tp_d1_skew DMD data skew – DMD_D(14:0),
DMD_SCTRL, DMD_LOADB, and DMD_TRC
signals relative to each other(3) 		50% reference points 0.2 ns
tp_clk_skew Clock skew – DMD_DCLK and DMD_SAC_CLK relative to each other 50% reference points 0.2 ns
tp_d2_skew DAD/SAC data skew - DMD_SAC_BUS,
DMD_DRC_OEZ(6), DMD_DRC_BUS,
and DMD_DRC_STRB signals relative to DMD_SAC_CLK		 50% reference points 0.2 ns
(1) This range includes the 200 ppm of the external oscillator (but no jitter).
(2) Assumes minimum DMD setup time = 1 ns and minimum DMD hold time = 1 ns
(3) Assumes DMD data routing skew = 0.1 ns max
(4) Output setup and hold numbers already account for controller clock jitter. Only routing skew and DMD setup/hold must be considered in system timing analysis.
(5) Assumes a 30-Ω series termination for all DMD interface signals (except DAD_DMD_OEZ)
(6) DMD_DAD_OEZ requires a 30- to 100-kΩ external pullup resistor connected to VCC18 to achieve proper timing.