JAJSFU7E December   2013  – March 2019 DLPC2607

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Typical Current and Power Dissipation
    6. 6.6  I/O Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  Parallel I/F Frame Timing Requirements
    9. 6.9  Parallel I/F General Timing Requirements
    10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
    11. 6.11 BT.656 I/F General Timing Requirements
    12. 6.12 100- to 120-Hz Operational Limitations
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 mDDR Memory Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
    4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Reference Clock
        2. 8.2.2.2 mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Hot-Plug Usage
        2. 8.2.3.2 Maximum Signal Transition Time
        3. 8.2.3.3 Configuration Control
        4. 8.2.3.4 White Point Correction Light Sensor
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 System Power I/O State Considerations
    4. 9.4 Power-Up Initialization Sequence
    5. 9.5 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  Internal ASIC PLL Power
      2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
      3. 10.1.3  SPI Signal Routing
      4. 10.1.4  mDDR Memory and DMD Interface Considerations
      5. 10.1.5  PCB Design
      6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
      7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
      8. 10.1.8  I/F Specific PCB Routing
      9. 10.1.9  Number of Layer Changes
      10. 10.1.10 Stubs
      11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 デバイスの項目表記
        1. 11.1.2.1 デバイス・マーキング
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 付録: パッケージ･オプション
      1. 12.1.1 パッケージ情報

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZVB|176
サーマルパッド・メカニカル・データ

6.15 mDDR Memory Interface Timing Requirements

The DLPC2607 controller mDDR memory interface consists of a 16-bit wide, mDDR interface (that is, LVCMOS signaling) operated at 133.33 MHz (nominal). (see (1)(2)(3))
MIN MAX UNIT
tCYCLE Cycle-time reference 7500 ps
tCH CK high pulse width(4) 2700 ps
tCL CK low pulse width(4) 2700 ps
tDQSH DQS high pulse width(4) 2700 ps
tDQSL DQS low pulse width(4) 2700 ps
tWAC CK to address and control outputs active –2870 2870 ps
tQAC CK to DQS output active 200 ps
tDAC DQS to DQ and DM output active –1225 1225 ps
tDQSRS Input (read) DQS and DQ skew(5) 1000 ps
(1) This includes the 200 ppm of the external oscillator (but no jitter).
(2) Output setup and hold numbers already account for controller clock jitter. Only routing skew and memory setup/hold must be considered in system timing analysis.
(3) Assumes a 30-Ω series termination on all signal lines.
(4) CK and DQS pulse duration specifications for the DLPC2607 assume it is interfacing to a 166-MHz mDDR device. Even though these memories are only operated at 133.33 MHz, according to memory vendors, the rated tCK specification (that is 6 ns) can be applied to determine minimum CK and DQS pulse duration requirements to the memory.
(5) Note that DQS must be within the tDQSRS read data-skew window, but need not be centered.
DLPC2607 parallel_frame_timing_dlps30.gifFigure 1. Parallel I/F Frame Timing
DLPC2607 parallel_general_timing_dlps30.gifFigure 2. Parallel and BT.656 I/F General Timing
DLPC2607 PDATA_bus_bit_mapping_dlps30.gifFigure 3. DLPC2607 PDATA Bus – BT.656 I/F Mode Bit Mapping (YCrCb 4:2:2 Source)
DLPC2607 flash_IF_timing_dlps030.gifFigure 4. Flash I/F Timing
DLPC2607 DMD_IF_timing_dlps030.gifFigure 5. DMD I/F Timing
DLPC2607 memory_address_control_timing_dlps30.gifFigure 6. mDRR Memory Address and Control Timing
DLPC2607 memory_write_data_timing_dlps30.gifFigure 7. mDRR Memory Write Dtat Timing
DLPC2607 memory_read_data_timing_dlps30.gifFigure 8. mDDR Memory Read Data Timing