JAJSGN4F August   2012  – February 2019 DLPC410

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Binary Pattern Data Path
        1. 8.3.1.1  DIN_A, DIN_B, DIN_C, DIN_D Input Data Buses
        2. 8.3.1.2  DCLKIN Input Clocks
        3. 8.3.1.3  DVALID Input Signals
        4. 8.3.1.4  DOUT_A, DOUT_B, DOUT_C, DOUT_D Output Data Buses
        5. 8.3.1.5  DCLKOUT Output Clocks
        6. 8.3.1.6  SCTRL Output Signals
        7. 8.3.1.7  Supported DMD Bus Sizes
        8. 8.3.1.8  Row Cycle definition
        9. 8.3.1.9  DLP9500 and DLP9500UV Input Data Formatting
        10. 8.3.1.10 DLP7000 and DLP7000UV Input Data Bus
        11. 8.3.1.11 DLP650LNIR Input Data Bus
      2. 8.3.2 Data Bus Operations
        1. 8.3.2.1 Row Addressing
        2. 8.3.2.2 Single Row Write Operation
        3. 8.3.2.3 No-Op Row Cycle Description
      3. 8.3.3 DMD Block Operations
        1. 8.3.3.1 Mirror Clocking Pulse (MCP)
        2. 8.3.3.2 Reset Active (RST_ACTIVE)
        3. 8.3.3.3 DMD Block Control Signals
          1. 8.3.3.3.1 Block Mode - BLK_MD1:0)
          2. 8.3.3.3.2 Block Address - BLK_AD(3:0)
          3. 8.3.3.3.3 Reset 2 Blocks - RST2BLK
        4. 8.3.3.4 DMD Block Operations
          1. 8.3.3.4.1 Global Reset (MCP) Consideration
      4. 8.3.4 Other Data Control Inputs
        1. 8.3.4.1 Complement Data
        2. 8.3.4.2 North/South Flip
      5. 8.3.5 Miscellaneous Control Inputs
        1. 8.3.5.1 ARST
        2. 8.3.5.2 CLKIN_R
        3. 8.3.5.3 DMD_A_RESET
        4. 8.3.5.4 Watchdog Timer Enable (WDT_ENABLE)
      6. 8.3.6 Miscellaneous Status Outputs
        1. 8.3.6.1 INIT_ACTIVE
        2. 8.3.6.2 DMD_Type(3:0)
        3. 8.3.6.3 DDC_VERSION(3:0)
        4. 8.3.6.4 LED0
        5. 8.3.6.5 LED1
        6. 8.3.6.6 DLPA200 Control Signals
        7. 8.3.6.7 ECM2M_TP_ (31:0)
    4. 8.4 Device Functional Modes
      1. 8.4.1 DLPC410 Initialization and Training
        1. 8.4.1.1 Initialization
        2. 8.4.1.2 input Data Interface (DIN) Training Pattern
      2. 8.4.2 DLPC410 Operational Modes
        1. 8.4.2.1 Single Block Mode
        2. 8.4.2.2 Single Block Phased Mode
        3. 8.4.2.3 Dual Block Mode
        4. 8.4.2.4 Quad Block Mode
        5. 8.4.2.5 Global Mode
        6. 8.4.2.6 DMD Park Mode
        7. 8.4.2.7 DMD Idle Mode
      3. 8.4.3 LOAD4 Functionality (enabled with DLPR410A)
        1. 8.4.3.1 Enabling LOAD4
        2. 8.4.3.2 Loading Data with LOAD4
        3. 8.4.3.3 Row Mapping with LOAD4
        4. 8.4.3.4 Using Block Clear with LOAD4
        5. 8.4.3.5 Timing Requirements for LOAD4
        6. 8.4.3.6 Global Binary Pattern Rate increases using LOAD4
        7. 8.4.3.7 Special LOAD4 considerations
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Description
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
      1. 9.3.1 Debugging Guidelines
      2. 9.3.2 Initialization
        1. 9.3.2.1 Calibration
        2. 9.3.2.2 DLPA200 Number 1 Initialization
        3. 9.3.2.3 DMD Initialization
          1. 9.3.2.3.1 DMD Device ID Check
          2. 9.3.2.3.2 DMD Device OK
        4. 9.3.2.4 DLPA200 Number 2 Initialization
        5. 9.3.2.5 Command Sequence Initialization
      3. 9.3.3 Image Display Issues
        1. 9.3.3.1 Present Data to DLPC410
        2. 9.3.3.2 Load Data to DMD
        3. 9.3.3.3 Mirror Clocking Pulse
  10. 10Power Supply Recommendations
    1. 10.1 Power Down Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLPC410 DMD Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
    3. 11.3 DLPC410 Chipset Connections
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイス・マーキング
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DLP|676
サーマルパッド・メカニカル・データ
発注情報

8.3.3.4 DMD Block Operations

Once a portion or all of the DMD is loaded with new data, the user typically requests a Block Operation to be performed. This operation causes the DLPC410 to initiate one of the many block related activities to a block or group of blocks to the DMD. Available Block operations are:

  • Block No-Op - user requests via BLK_MD(1:0) = "00" that no block operations are to take place in this row cycle. This is typically the case for row cycles used for data loading purposes only without any block operations.
  • Block Clear Request - user requests a single block to be cleared causing all SRAM cells within that block to be reset to logic '0'.
  • Single Block Reset Request - user requests a single DMD block be provided a Reset (MCP) signal to cause the micromirrors within that block to update to their new values.
  • Dual Block Reset Request - user requests two sequential DMD blocks be provided Reset (MCP) signals to cause the micromirrors within those blocks to update to their new values.
  • Quad Block Reset Request - user requests four sequential DMD blocks be provided Reset (MCP) signals to cause the micromirrors within those blocks to update to their new values.
  • Global Reset Request - user requests all DMD blocks be provided Reset (MCP) signals to cause all DMD micromirrors to update to their new values.
  • DMD Park (Float) Request - user requests all DMD micromirrors be provided special Parking Reset (MCP) signals causing the micromirrors within those blocks to relax to their unbiased state. This request is intended to place the micromirrors in the Parked state prior to power removal (shutdown).


Mirror blocks are addressed using the Block Address (BLK_AD[3:0]) signals for application of either a Mirror Clocking Pulse (Reset) or a Memory Clear operation by asserting the block control signals of Table 14 at the start of each row data load. RST2BLK, Block Mode (BLK_MD[1:0]), and BLK_AD[3:0] define the requested operation as shown in Table 14 and designate which mirror block or mirror blocks are issued a Mirror Clocking Pulse or are Cleared. The number of DMD blocks and BLOCKS/ROW is unique to each DMD - refer to the individual DMD data sheets for DMD block definition.

Table 14. Block Control Signals and Operations

RST2BLK BLK_MD(1:0) BLK_AD(3:0) OPERATION OPERATION TYPE
x 00 xxxx None Block No-OP
x 01 0000 Clear block 00 Block Clear Request(1)(2)
x 01 0001 Clear block 01
x 01 0010 Clear block 02
x 01 0011 Clear block 03
x 01 0100 Clear block 04
x 01 0101 Clear block 05
x 01 0110 Clear block 06
x 01 0111 Clear block 07
x 01 1000 Clear block 08
x 01 1001 Clear block 09
x 01 1010 Clear block 10
x 01 1011 Clear block 11
x 01 1100 Clear block 12
x 01 1101 Clear block 13
x 01 1110 Clear block 14
x 01 1111 Clear block 15
x 10 0000 Reset block 00 Single Block Reset Request
x 10 0001 Reset block 01
x 10 0010 Reset block 02
x 10 0011 Reset block 03
x 10 0100 Reset block 04
x 10 0101 Reset block 05
x 10 0110 Reset block 06
x 10 0111 Reset block 07
x 10 1000 Reset block 08
x 10 1001 Reset block 09
x 10 1010 Reset block 10
x 10 1011 Reset block 11
x 10 1100 Reset block 12
x 10 1101 Reset block 13
x 10 1110 Reset block 14
x 10 1111 Reset block 15
0 11 0000 Reset blocks 00-01 Dual Block Reset Request
0 11 0001 Reset blocks 02-03
0 11 0010 Reset blocks 04-05
0 11 0011 Reset blocks 06-07
0 11 0100 Reset blocks 08-09
0 11 0101 Reset blocks 10-11
0 11 0110 Reset blocks 12-13
0 11 0111 Reset blocks 14-15
1 11 000x Reset blocks 00-03 Quad Block Reset Request
1 11 001x Reset blocks 04-07
1 11 010x Reset blocks 08-11
1 11 011x Reset blocks 12-15
x 11 10xx Reset blocks 00-15 Global Reset Request
x 11 11xx Float blocks 00-15 DMD Park Request
(1) Each Block Clear operation for DLP650LNIR and DLP7000(UV) DMDs will clear all SRAM cells of one DMD block (reset to '0') within one row cycle duration.
(2) Each Block Clear operation for DLP9500(UV) DMDs must be followed by two No-Op row cycles. To clear one DMD Block, one Block Clear Request row cycle followed by two consecutive No Op row cycles are required. In total, 15 Block Clear Request row cycles and 30 No-Ops are required to clear the entire 15 block DMD array.

Block operations cause the DMD micromirrors to transition to their next state. Some notes and restrictions regarding block operations are:

  • A Block No-Op row cycle causes no new block operations to occur. Block No-Op row cycles can be used to provide extended time for a previous operation.
  • The Block Clear operation resets all SRAM pixels in the designated block to logic zero during the current row cycle.
  • It is not necessary to Clear a block if it will be reloaded with new data (just like a normal memory cell).
  • It is not possible to Clear a block while writing to a different block.
  • It is possible to issue a Mirror Clocking Pulse to a block while data loading a different block.
  • The DLP9500 and DLP9500UV DMDs have 15 blocks (block 0 – block 14). Block operations on block 15 have no function for this DMD.
  • RST2BLK should be set to one value and not adjusted during normal system operation. A change in RST2BLK is not immediately effective and will require more than one row load cycle to complete.