JAJSGN4F August   2012  – February 2019 DLPC410

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Binary Pattern Data Path
        1. 8.3.1.1  DIN_A, DIN_B, DIN_C, DIN_D Input Data Buses
        2. 8.3.1.2  DCLKIN Input Clocks
        3. 8.3.1.3  DVALID Input Signals
        4. 8.3.1.4  DOUT_A, DOUT_B, DOUT_C, DOUT_D Output Data Buses
        5. 8.3.1.5  DCLKOUT Output Clocks
        6. 8.3.1.6  SCTRL Output Signals
        7. 8.3.1.7  Supported DMD Bus Sizes
        8. 8.3.1.8  Row Cycle definition
        9. 8.3.1.9  DLP9500 and DLP9500UV Input Data Formatting
        10. 8.3.1.10 DLP7000 and DLP7000UV Input Data Bus
        11. 8.3.1.11 DLP650LNIR Input Data Bus
      2. 8.3.2 Data Bus Operations
        1. 8.3.2.1 Row Addressing
        2. 8.3.2.2 Single Row Write Operation
        3. 8.3.2.3 No-Op Row Cycle Description
      3. 8.3.3 DMD Block Operations
        1. 8.3.3.1 Mirror Clocking Pulse (MCP)
        2. 8.3.3.2 Reset Active (RST_ACTIVE)
        3. 8.3.3.3 DMD Block Control Signals
          1. 8.3.3.3.1 Block Mode - BLK_MD1:0)
          2. 8.3.3.3.2 Block Address - BLK_AD(3:0)
          3. 8.3.3.3.3 Reset 2 Blocks - RST2BLK
        4. 8.3.3.4 DMD Block Operations
          1. 8.3.3.4.1 Global Reset (MCP) Consideration
      4. 8.3.4 Other Data Control Inputs
        1. 8.3.4.1 Complement Data
        2. 8.3.4.2 North/South Flip
      5. 8.3.5 Miscellaneous Control Inputs
        1. 8.3.5.1 ARST
        2. 8.3.5.2 CLKIN_R
        3. 8.3.5.3 DMD_A_RESET
        4. 8.3.5.4 Watchdog Timer Enable (WDT_ENABLE)
      6. 8.3.6 Miscellaneous Status Outputs
        1. 8.3.6.1 INIT_ACTIVE
        2. 8.3.6.2 DMD_Type(3:0)
        3. 8.3.6.3 DDC_VERSION(3:0)
        4. 8.3.6.4 LED0
        5. 8.3.6.5 LED1
        6. 8.3.6.6 DLPA200 Control Signals
        7. 8.3.6.7 ECM2M_TP_ (31:0)
    4. 8.4 Device Functional Modes
      1. 8.4.1 DLPC410 Initialization and Training
        1. 8.4.1.1 Initialization
        2. 8.4.1.2 input Data Interface (DIN) Training Pattern
      2. 8.4.2 DLPC410 Operational Modes
        1. 8.4.2.1 Single Block Mode
        2. 8.4.2.2 Single Block Phased Mode
        3. 8.4.2.3 Dual Block Mode
        4. 8.4.2.4 Quad Block Mode
        5. 8.4.2.5 Global Mode
        6. 8.4.2.6 DMD Park Mode
        7. 8.4.2.7 DMD Idle Mode
      3. 8.4.3 LOAD4 Functionality (enabled with DLPR410A)
        1. 8.4.3.1 Enabling LOAD4
        2. 8.4.3.2 Loading Data with LOAD4
        3. 8.4.3.3 Row Mapping with LOAD4
        4. 8.4.3.4 Using Block Clear with LOAD4
        5. 8.4.3.5 Timing Requirements for LOAD4
        6. 8.4.3.6 Global Binary Pattern Rate increases using LOAD4
        7. 8.4.3.7 Special LOAD4 considerations
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Description
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
      1. 9.3.1 Debugging Guidelines
      2. 9.3.2 Initialization
        1. 9.3.2.1 Calibration
        2. 9.3.2.2 DLPA200 Number 1 Initialization
        3. 9.3.2.3 DMD Initialization
          1. 9.3.2.3.1 DMD Device ID Check
          2. 9.3.2.3.2 DMD Device OK
        4. 9.3.2.4 DLPA200 Number 2 Initialization
        5. 9.3.2.5 Command Sequence Initialization
      3. 9.3.3 Image Display Issues
        1. 9.3.3.1 Present Data to DLPC410
        2. 9.3.3.2 Load Data to DMD
        3. 9.3.3.3 Mirror Clocking Pulse
  10. 10Power Supply Recommendations
    1. 10.1 Power Down Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLPC410 DMD Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
    3. 11.3 DLPC410 Chipset Connections
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイス・マーキング
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DLP|676
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

ZYR Package
676-Pin FCBGA
Bottom View
DLPC410 DLPC410 Pinout.pngFigure 1. DLPC410 Pinout Diagram

Pin Functions

PIN TYPE SIGNAL TERMINATION
/NOTES		 ACTIVE
(Hi or Lo)		 CLOCK DATA
RATE		 DESCRIPTION
NAME NO.
APPS_CNTL_DPN F7 - - This pair connected with 100 Ω resistor between pair. - - Not Used
APPS_CNTL_DPP E7 - - - - Not Used
ARST AC13 I LVCMOS25_S_12_I Lo - DLPC410 Reset
AVDD_0 M14 - - Not used - connect to Ground (no name in Reference Design) - - Xilinx System Monitor analog supply - (not used - must be connected to ground)
AVSS_0 M13 - - Not used - connect to Ground (no name in Reference Design) - - Xilinx System Monitor analog ground - (not used - must be connected to ground)
BLKAD_0 E12 I LVCMOS25_S_12_I Hi = 1 DDC_DCLK_[A,B,C,D] Block Address bit 0
BLKAD_1 D13 I LVCMOS25_S_12_I Hi = 1 DDC_DCLK_[A,B,C,D] Block Address bit 1
BLKAD_2 E13 I LVCMOS25_S_12_I Hi = 1 DDC_DCLK_[A,B,C,D] Block Address bit 2
BLKAD_3 F13 I LVCMOS25_S_12_I Hi = 1 DDC_DCLK_[A,B,C,D] Block Address bit 3
BLKMD_0 H13 I LVCMOS25_S_12_I Hi = 1 DDC_DCLK_[A,B,C,D] Block Mode Bit 0
BLKMD_1 H14 I LVCMOS25_S_12_I Hi = 1 DDC_DCLK_[A,B,C,D] Block Mode Bit 1
CLKIN_R AD13 I LVCMOS25_S_12_I - Reference Clock Reference Clock
COMP_DATA G19 I LVCMOS25_S_12_I Hi DDC_DCLK_[A,B,C,D] Compliment Data (0 <--> 1)
CS_B_0 N18 - - 1 kΩ pulldown to ground Lo - Xilinx Config
D_OUT_BUSY_0 W11 - NC Do not connect - - Not Used
DAD_A_ADDR0 E1 O LVCMOS25_F_12_O Connected to DLPA200 number 1 Address 0 pin Hi = 1 - DLPA200 Number 1 Reset Block bit 0
DAD_A_ADDR1 E2 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 Address 1 pin Hi = 1 - DLPA200 Number 1 Reset Block bit 1
DAD_A_ADDR2 E3 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 Address 2 pin Hi = 1 - DLPA200 Number 1 Reset Block bit 2
DAD_A_ADDR3 F3 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 Address 3 pin Hi = 1 - DLPA200 Number 1 Reset Block bit 3
DAD_A_MODE0 C1 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 Mode 0 pin Hi = 1 - DLPA200 Number 1Mode bit 0
DAD_A_MODE1 D1 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 Mode 1 pin Hi = 1 - DLPA200 Number 1 Mode bit 1
DAD_A_SCPEN AE3 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 SCPEN pin Lo - DLPA200 Number 1 SCP Communication Enable
DAD_A_SEL0 AB12 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 SEL 0 pin Hi = 1 - DLPA200 Number 1 Address bit 0
DAD_A_SEL1 AC12 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 SEL 1 pin Hi = 1 - DLPA200 Number 1 Address bit 1
DAD_A_STROBE AF3 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 STROBE pin Hi - DLPA200 Number 1 Transition Strobe
DAD_B_ADDR0 E26 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 Address 1 pin Hi = 1 - DLPA200 Number 2 Reset Block bit 0
DAD_B_ADDR1 E25 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 Address 2 pin Hi = 1 - DLPA200 Number 2 Reset Block bit 1
DAD_B_ADDR2 F25 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 Address 3 pin Hi = 1 - DLPA200 Number 2 Reset Block bit 2
DAD_B_ADDR3 F24 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 Address 0 pin Hi = 1 - DLPA200 Number 2 Reset Block bit 3
DAD_B_MODE0 D26 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 Mode 0 pin Hi = 1 - DLPA200 Number 2 Mode bit 0
DAD_B_MODE1 D25 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 Mode 1 pin Hi = 1 - DLPA200 Number 2 Mode bit 1
DAD_B_SCPEN AB19 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 SCPEN pin Lo - DLPA200 Number 2 SCP Communication Enable
DAD_B_SEL0 R22 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 SEL 0 pin Hi = 1 - DLPA200 Number 2 Address bit 0
DAD_B_SEL1 R23 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 SEL 1 pin Hi = 1 - DLPA200 Number 2 Address bit 1
DAD_B_STROBE AB20 O LVCMOS25_F_12_O Connected to DLPA200 Number 2 STROBE pin Hi - DLPA200 Number 2 Transition Strobe
DAD_INIT AF4 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 and Number 2 RESET pin Hi - DLPA200 Number 1 / Number 2 Init
DAD_OE AF5 O LVCMOS25_F_12_O Connected to DLPA200 Number 1 and Number 2 OE pin Lo - DLPA200 Number 1 / Number 2 Output Enable
DDC_B11_VRN L23 - REFERENCE 51.1 Ω pullup to 2.5 V - - Reference Voltage
DDC_B11_VRP L22 - REFERENCE 51.1 Ω pulldown to ground - - Reference Ground
DDC_B12_VRN M5 - REFERENCE 51.1 Ω pullup to 2.5 V - - Reference Voltage
DDC_B12_VRP M6 - REFERENCE 51.1 Ω pulldown to ground - - Reference Ground
DDC_B15_VRN D23 - REFERENCE 51.1 Ω pullup to 2.5 V - - Reference Voltage
DDC_B15_VRP C22 - REFERENCE 51.1 Ω pulldown to ground - - Reference Ground
DDC_B16_VRN A4 - REFERENCE 51.1 Ω pullup to 2.5 V - - Reference Voltage
DDC_B16_VRP A5 - REFERENCE 51.1 Ω pulldown to ground - - Reference Ground
DDC_DCLK_A_DPN B21 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - - Bank A Input Clock (Neg)
DDC_DCLK_A_DPP C21 I LVDS_25_I - - Bank A Input Clock (Pos)
DDC_DCLK_B_DPN A7 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - - Bank B Input Clock (Neg)
DDC_DCLK_B_DPP B7 I LVDS_25_I - - Bank B Input Clock (Pos)
DDC_DCLK_C_DPN K20 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - - Bank C Input Clock (Neg)
DDC_DCLK_C_DPP K21 I LVDS_25_I - - Bank C Input Clock (Pos)
DDC_DCLK_D_DPN L5 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - - Bank D Input Clock (Neg)
DDC_DCLK_D_DPP K5 I LVDS_25_I - - Bank D Input Clock (Pos)
DDC_DCLKOUT_A_DPN N1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - - Bank A Output Clock (Neg)
DDC_DCLKOUT_A_DPP M1 O LVDS_25_O - - Bank A Output Clock (Pos)
DDC_DCLKOUT_B_DPN Y5 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - - Bank B Output Clock (Neg)
DDC_DCLKOUT_B_DPP Y6 O LVDS_25_O - - Bank B Output Clock (Pos)
DDC_DCLKOUT_C_DPN AA22 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - - Bank C Output Clock (Neg)
DDC_DCLKOUT_C_DPP AB22 O LVDS_25_O - - Bank C Output Clock (Pos)
DDC_DCLKOUT_D_DPN M26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - - Bank D Output Clock (Neg)
DDC_DCLKOUT_D_DPP M25 O LVDS_25_O - - Bank D Output Clock (Pos)
DDC_DIN_A0_DPN A15 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 0 Input (Neg)
DDC_DIN_A0_DPP A14 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 0 Input (Pos)
DDC_DIN_A1_DPN B14 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 1 Input (Neg)
DDC_DIN_A1_DPP C14 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 1 Input (Pos)
DDC_DIN_A2_DPN B16 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 2 Input (Neg)
DDC_DIN_A2_DPP B15 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 2 Input (Pos)
DDC_DIN_A3_DPN C16 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 3 Input (Neg)
DDC_DIN_A3_DPP D16 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 3 Input (Pos)
DDC_DIN_A4_DPN A17 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 4 Input (Neg)
DDC_DIN_A4_DPP B17 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 4 Input (Pos)
DDC_DIN_A5_DPN C17 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 5 Input (Neg)
DDC_DIN_A5_DPP D18 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 5 Input (Pos)
DDC_DIN_A6_DPN A19 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 6 Input (Neg)
DDC_DIN_A6_DPP A18 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 6 Input (Pos)
DDC_DIN_A7_DPN C18 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 7 Input (Neg)
DDC_DIN_A7_DPP B19 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 7 Input (Pos)
DDC_DIN_A8_DPN D19 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 8 Input (Neg)
DDC_DIN_A8_DPP C19 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 8 Input (Pos)
DDC_DIN_A9_DPN B20 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 9 Input (Neg)
DDC_DIN_A9_DPP A20 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 9 Input (Pos)
DDC_DIN_A10_DPN A22 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 10 Input (Neg)
DDC_DIN_A10_DPP B22 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 10 Input (Pos)
DDC_DIN_A11_DPN A24 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 11 Input (Neg)
DDC_DIN_A11_DPP A23 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 11 Input (Pos)
DDC_DIN_A12_DPN C23 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 12 Input (Neg)
DDC_DIN_A12_DPP B24 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 12 Input (Pos)
DDC_DIN_A13_DPN C24 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 13 Input (Neg)
DDC_DIN_A13_DPP D24 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 13 Input (Pos)
DDC_DIN_A14_DPN A25 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 14 Input (Neg)
DDC_DIN_A14_DPP B25 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 14 Input (Pos)
DDC_DIN_A15_DPN C26 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A DDR Data A bit 15 Input (Neg)
DDC_DIN_A15_DPP B26 I LVDS_25_I - DDC_DCLK_A DDR Data A bit 15 Input (Pos)
DDC_DIN_B0_DPN A12 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 0 Input (Neg)
DDC_DIN_B0_DPP A13 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 0 Input (Pos)
DDC_DIN_B1_DPN B12 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 1 Input (Neg)
DDC_DIN_B1_DPP C13 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 1 Input (Pos)
DDC_DIN_B2_DPN D10 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 2 Input (Neg)
DDC_DIN_B2_DPP D11 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 2 Input (Pos)
DDC_DIN_B3_DPN C12 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 3 Input (Neg)
DDC_DIN_B3_DPP C11 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 3 Input (Pos)
DDC_DIN_B4_DPN A10 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 4 Input (Neg)
DDC_DIN_B4_DPP B11 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 4 Input (Pos)
DDC_DIN_B5_DPN D9 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 5 Input (Neg)
DDC_DIN_B5_DPP C9 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 5 Input (Pos)
DDC_DIN_B6_DPN B10 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 6 Input (Neg)
DDC_DIN_B6_DPP B9 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 6 Input (Pos)
DDC_DIN_B7_DPN A8 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 7 Input (Neg)
DDC_DIN_B7_DPP A9 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 7 Input (Pos)
DDC_DIN_B8_DPN D6 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 8 Input (Neg)
DDC_DIN_B8_DPP D5 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 8 Input (Pos)
DDC_DIN_B9_DPN C7 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 9 Input (Neg)
DDC_DIN_B9_DPP C6 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 9 Input (Pos)
DDC_DIN_B10_DPN B6 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 10 Input (Neg)
DDC_DIN_B10_DPP B5 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 10 Input (Pos)
DDC_DIN_B11_DPN D4 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 11 Input (Neg)
DDC_DIN_B11_DPP D3 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 11 Input (Pos)
DDC_DIN_B12_DPN B4 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 12 Input (Neg)
DDC_DIN_B12_DPP C4 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 12 Input (Pos)
DDC_DIN_B13_DPN C3 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 13 Input (Neg)
DDC_DIN_B13_DPP C2 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 13 Input (Pos)
DDC_DIN_B14_DPN A3 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 14 Input (Neg)
DDC_DIN_B14_DPP A2 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 14 Input (Pos)
DDC_DIN_B15_DPN B2 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B DDR Data B bit 15 Input (Neg)
DDC_DIN_B15_DPP B1 I LVDS_25_I - DDC_DCLK_B DDR Data B bit 15 Input (Pos)
DDC_DIN_C0_DPN E20 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 0 Input (Neg)
DDC_DIN_C0_DPP E21 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 0 Input (Pos)
DDC_DIN_C1_DPN F20 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 1 Input (Neg)
DDC_DIN_C1_DPP G20 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 1 Input (Pos)
DDC_DIN_C2_DPN H19 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 2 Input (Neg)
DDC_DIN_C2_DPP J19 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 2 Input (Pos)
DDC_DIN_C3_DPN E23 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 3 Input (Neg)
DDC_DIN_C3_DPP E22 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 3 Input (Pos)
DDC_DIN_C4_DPN F23 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 4 Input (Neg)
DDC_DIN_C4_DPP F22 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 4 Input (Pos)
DDC_DIN_C5_DPN G22 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 5 Input (Neg)
DDC_DIN_C5_DPP G21 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 5 Input (Pos)
DDC_DIN_C6_DPN J20 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 6 Input (Neg)
DDC_DIN_C6_DPP J21 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 6 Input (Pos)
DDC_DIN_C7_DPN H22 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 7 Input (Neg)
DDC_DIN_C7_DPP H21 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 7 Input (Pos)
DDC_DIN_C8_DPN J23 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 8 Input (Neg)
DDC_DIN_C8_DPP H23 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 8 Input (Pos)
DDC_DIN_C9_DPN K22 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 9 Input (Neg)
DDC_DIN_C9_DPP K23 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 9 Input (Pos)
DDC_DIN_C10_DPN M19 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 10 Input (Neg)
DDC_DIN_C10_DPP M20 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 10 Input (Pos)
DDC_DIN_C11_DPN M21 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 11 Input (Neg)
DDC_DIN_C11_DPP M22 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 11 Input (Pos)
DDC_DIN_C12_DPN N19 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 12 Input (Neg)
DDC_DIN_C12_DPP P19 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 12 Input (Pos)
DDC_DIN_C13_DPN N21 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 13 Input (Neg)
DDC_DIN_C13_DPP N22 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 13 Input (Pos)
DDC_DIN_C14_DPN P20 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 14 Input (Neg)
DDC_DIN_C14_DPP P21 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 14 Input (Pos)
DDC_DIN_C15_DPN N23 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C DDR Data C bit 15 Input (Neg)
DDC_DIN_C15_DPP P23 I LVDS_25_I - DDC_DCLK_C DDR Data C bit 15 Input (Pos)
DDC_DIN_D0_DPN T3 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 0 Input (Neg)
DDC_DIN_D0_DPP R3 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 0 Input (Pos)
DDC_DIN_D1_DPN R5 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 1 Input (Neg)
DDC_DIN_D1_DPP R6 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 1 Input (Pos)
DDC_DIN_D2_DPN R7 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 2 Input (Neg)
DDC_DIN_D2_DPP P6 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 2 Input (Pos)
DDC_DIN_D3_DPN N3 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 3 Input (Neg)
DDC_DIN_D3_DPP P3 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 3 Input (Pos)
DDC_DIN_D4_DPN P4 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 4 Input (Neg)
DDC_DIN_D4_DPP P5 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 4 Input (Pos)
DDC_DIN_D5_DPN N6 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 5 Input (Neg)
DDC_DIN_D5_DPP N7 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 5 Input (Pos)
DDC_DIN_D6_DPN N4 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 6 Input (Neg)
DDC_DIN_D6_DPP M4 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 6 Input (Pos)
DDC_DIN_D7_DPN M7 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 7 Input (Neg)
DDC_DIN_D7_DPP L7 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 7 Input (Pos)
DDC_DIN_D8_DPN K7 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 8 Input (Neg)
DDC_DIN_D8_DPP K6 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 8 Input (Pos)
DDC_DIN_D9_DPN J4 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 9 Input (Neg)
DDC_DIN_D9_DPP J5 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 9 Input (Pos)
DDC_DIN_D10_DPN H7 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 10 Input (Neg)
DDC_DIN_D10_DPP J6 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 10 Input (Pos)
DDC_DIN_D11_DPN G4 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 11 Input (Neg)
DDC_DIN_D11_DPP H4 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 11 Input (Pos)
DDC_DIN_D12_DPN G5 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 12 Input (Neg)
DDC_DIN_D12_DPP H6 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 12 Input (Pos)
DDC_DIN_D13_DPN G7 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 13 Input (Neg)
DDC_DIN_D13_DPP G6 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 13 Input (Pos)
DDC_DIN_D14_DPN F4 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 14 Input (Neg)
DDC_DIN_D14_DPP F5 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 14 Input (Pos)
DDC_DIN_D15_DPN E5 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D DDR Data D bit 15 Input (Neg)
DDC_DIN_D15_DPP E6 I LVDS_25_I - DDC_DCLK_D DDR Data D bit 15 Input (Pos)
DDC_DOUT_A0_DPN AE2 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 0 Output (Neg)
DDC_DOUT_A0_DPP AF2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 0 Output (Pos)
DDC_DOUT_A1_DPN AD1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 1 Output (Neg)
DDC_DOUT_A1_DPP AE1 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 1 Output (Pos)
DDC_DOUT_A2_DPN AC1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 2 Output (Neg)
DDC_DOUT_A2_DPP AC2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 2 Output (Pos)
DDC_DOUT_A3_DPN AB1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 3 Output (Neg)
DDC_DOUT_A3_DPP AB2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 3 Output (Pos)
DDC_DOUT_A4_DPN Y2 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 4 Output (Neg)
DDC_DOUT_A4_DPP AA2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 4 Output (Pos)
DDC_DOUT_A5_DPN W1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 5 Output (Neg)
DDC_DOUT_A5_DPP Y1 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 5 Output (Pos)
DDC_DOUT_A6_DPN V1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 6 Output (Neg)
DDC_DOUT_A6_DPP V2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 6 Output (Pos)
DDC_DOUT_A7_DPN U1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 7 Output (Neg)
DDC_DOUT_A7_DPP U2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 7 Output (Pos)
DDC_DOUT_A8_DPN R2 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 8 Output (Neg)
DDC_DOUT_A8_DPP T2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 8 Output (Pos)
DDC_DOUT_A9_DPN N2 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 9 Output (Neg)
DDC_DOUT_A9_DPP M2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 9 Output (Pos)
DDC_DOUT_A10_DPN K1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 10 Output (Neg)
DDC_DOUT_A10_DPP L2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 10 Output (Pos)
DDC_DOUT_A11_DPN K2 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 11 Output (Neg)
DDC_DOUT_A11_DPP K3 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 11 Output (Pos)
DDC_DOUT_A12_DPN J3 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 12 Output (Neg)
DDC_DOUT_A12_DPP H3 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 12 Output (Pos)
DDC_DOUT_A13_DPN H2 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 13 Output (Neg)
DDC_DOUT_A13_DPP J1 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 13 Output (Pos)
DDC_DOUT_A14_DPN H1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 14 Output (Neg)
DDC_DOUT_A14_DPP G1 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 14 Output (Pos)
DDC_DOUT_A15_DPN G2 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Data A bit 15 Output (Neg)
DDC_DOUT_A15_DPP F2 O LVDS_25_O - DDC_DCLKOUT_A DDR Data A bit 15 Output (Pos)
DDC_DOUT_B0_DPN AE5 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 0 Output (Neg)
DDC_DOUT_B0_DPP AE6 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 0 Output (Pos)
DDC_DOUT_B1_DPN AD3 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 1 Output (Neg)
DDC_DOUT_B1_DPP AD4 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 1 Output (Pos)
DDC_DOUT_B2_DPN AD5 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 2 Output (Neg)
DDC_DOUT_B2_DPP AD6 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 2 Output (Pos)
DDC_DOUT_B3_DPN AC3 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 3 Output (Neg)
DDC_DOUT_B3_DPP AC4 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 3 Output (Pos)
DDC_DOUT_B4_DPN AB5 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 4 Output (Neg)
DDC_DOUT_B4_DPP AB6 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 4 Output (Pos)
DDC_DOUT_B5_DPN AB7 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 5 Output (Neg)
DDC_DOUT_B5_DPP AC6 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 5 Output (Pos)
DDC_DOUT_B6_DPN AA5 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 6 Output (Neg)
DDC_DOUT_B6_DPP AA4 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 6 Output (Pos)
DDC_DOUT_B7_DPN AA7 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 7 Output (Neg)
DDC_DOUT_B7_DPP Y7 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 7 Output (Pos)
DDC_DOUT_B8_DPN Y3 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 8 Output (Neg)
DDC_DOUT_B8_DPP W3 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 8 Output (Pos)
DDC_DOUT_B9_DPN W4 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 9 Output (Neg)
DDC_DOUT_B9_DPP V4 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 9 Output (Pos)
DDC_DOUT_B10_DPN W6 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 10 Output (Neg)
DDC_DOUT_B10_DPP W5 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 10 Output (Pos)
DDC_DOUT_B11_DPN V7 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 11 Output (Neg)
DDC_DOUT_B11_DPP V6 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 11 Output (Pos)
DDC_DOUT_B12_DPN U4 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 12 Output (Neg)
DDC_DOUT_B12_DPP V3 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 12 Output (Pos)
DDC_DOUT_B13_DPN T4 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 13 Output (Neg)
DDC_DOUT_B13_DPP T5 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 13 Output (Pos)
DDC_DOUT_B14_DPN U6 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 14 Output (Neg)
DDC_DOUT_B14_DPP U5 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 14 Output (Pos)
DDC_DOUT_B15_DPN U7 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Data B bit 15 Output (Neg)
DDC_DOUT_B15_DPP T7 O LVDS_25_O - DDC_DCLKOUT_B DDR Data B bit 15 Output (Pos)
DDC_DOUT_C0_DPN T22 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 0 Output (Neg)
DDC_DOUT_C0_DPP T23 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 0 Output (Pos)
DDC_DOUT_C1_DPN R20 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 1 Output (Neg)
DDC_DOUT_C1_DPP R21 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 1 Output (Pos)
DDC_DOUT_C2_DPN T19 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 2 Output (Neg)
DDC_DOUT_C2_DPP T20 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 2 Output (Pos)
DDC_DOUT_C3_DPN U21 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 3 Output (Neg)
DDC_DOUT_C3_DPP U22 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 3 Output (Pos)
DDC_DOUT_C4_DPN U20 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 4 Output (Neg)
DDC_DOUT_C4_DPP U19 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 4 Output (Pos)
DDC_DOUT_C5_DPN V23 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 5 Output (Neg)
DDC_DOUT_C5_DPP V24 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 5 Output (Pos)
DDC_DOUT_C6_DPN V22 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 6 Output (Neg)
DDC_DOUT_C6_DPP V21 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 6 Output (Pos)
DDC_DOUT_C7_DPN W19 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 7 Output (Neg)
DDC_DOUT_C7_DPP V19 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 7 Output (Pos)
DDC_DOUT_C8_DPN W23 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 8 Output (Neg)
DDC_DOUT_C8_DPP W24 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 8 Output (Pos)
DDC_DOUT_C9_DPN Y22 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 9 Output (Neg)
DDC_DOUT_C9_DPP Y23 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 9 Output (Pos)
DDC_DOUT_C10_DPN Y20 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 10 Output (Neg)
DDC_DOUT_C10_DPP Y21 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 10 Output (Pos)
DDC_DOUT_C11_DPN AA24 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 11 Output (Neg)
DDC_DOUT_C11_DPP AA23 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 11 Output (Pos)
DDC_DOUT_C12_DPN AA19 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 12 Output (Neg)
DDC_DOUT_C12_DPP AA20 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 12 Output (Pos)
DDC_DOUT_C13_DPN AC24 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 13 Output (Neg)
DDC_DOUT_C13_DPP AB24 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 13 Output (Pos)
DDC_DOUT_C14_DPN AC19 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 14 Output (Neg)
DDC_DOUT_C14_DPP AD19 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 14 Output (Pos)
DDC_DOUT_C15_DPN AC22 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Data C bit 15 Output (Neg)
DDC_DOUT_C15_DPP AC23 O LVDS_25_O - DDC_DCLKOUT_C DDR Data C bit 15 Output (Pos)
DDC_DOUT_D0_DPN AB26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 0 Output (Neg)
DDC_DOUT_D0_DPP AC26 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 0 Output (Pos)
DDC_DOUT_D1_DPN AA25 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 1 Output (Neg)
DDC_DOUT_D1_DPP AB25 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 1 Output (Pos)
DDC_DOUT_D2_DPN Y26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 2 Output (Neg)
DDC_DOUT_D2_DPP Y25 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 2 Output (Pos)
DDC_DOUT_D3_DPN W26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 3 Output (Neg)
DDC_DOUT_D3_DPP W25 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 3 Output (Pos)
DDC_DOUT_D4_DPN U26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 4 Output (Neg)
DDC_DOUT_D4_DPP V26 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 4 Output (Pos)
DDC_DOUT_D5_DPN U25 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 5 Output (Neg)
DDC_DOUT_D5_DPP U24 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 5 Output (Pos)
DDC_DOUT_D6_DPN T25 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 6 Output (Neg)
DDC_DOUT_D6_DPP T24 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 6 Output (Pos)
DDC_DOUT_D7_DPN R26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 7 Output (Neg)
DDC_DOUT_D7_DPP R25 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 7 Output (Pos)
DDC_DOUT_D8_DPN P24 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 8 Output (Neg)
DDC_DOUT_D8_DPP P25 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 8 Output (Pos)
DDC_DOUT_D9_DPN N24 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 9 Output (Neg)
DDC_DOUT_D9_DPP M24 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 9 Output (Pos)
DDC_DOUT_D10_DPN L25 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 10 Output (Neg)
DDC_DOUT_D10_DPP L24 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 10 Output (Pos)
DDC_DOUT_D11_DPN K26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 11 Output (Neg)
DDC_DOUT_D11_DPP K25 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 11 Output (Pos)
DDC_DOUT_D12_DPN J26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 12 Output (Neg)
DDC_DOUT_D12_DPP J25 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 12 Output (Pos)
DDC_DOUT_D13_DPN J24 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 13 Output (Neg)
DDC_DOUT_D13_DPP H24 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 13 Output (Pos)
DDC_DOUT_D14_DPN H26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 14 Output (Neg)
DDC_DOUT_D14_DPP G26 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 14 Output (Pos)
DDC_DOUT_D15_DPN G25 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Data D bit 15 Output (Neg)
DDC_DOUT_D15_DPP G24 O LVDS_25_O - DDC_DCLKOUT_D DDR Data D bit 15 Output (Pos)
DDC_M0 W18 - NC 4.7 kΩ pullup to 2.5V Hi - Xilinx Configuration
DDC_M1 Y17 - NC 4.7 kΩ pullup to 2.5V Hi - Xilinx Configuration
DDC_M2 V18 - NC 4.7 kΩ pullup to 2.5V Hi - Xilinx Configuration
DDC_SCTRL_AN R1 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_A DDR Bank A Serial Control Data (Neg)
DDC_SCTRL_AP P1 O LVDS_25_O - DDC_DCLKOUT_A DDR Bank A Serial Control Data (Pos)
DDC_SCTRL_BN AA3 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_B DDR Bank B Serial Control Data (Neg)
DDC_SCTRL_BP AB4 O LVDS_25_O - DDC_DCLKOUT_B DDR Bank B Serial Control Data (Pos)
DDC_SCTRL_CN W20 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_C DDR Bank C Serial Control Data (Neg)
DDC_SCTRL_CP W21 O LVDS_25_O - DDC_DCLKOUT_C DDR Bank C Serial Control Data (Pos)
DDC_SCTRL_DN N26 O LVDS_25 Pair connected to DMD (LVDS terminated internally in DMD - 100 Ω) - DDC_DCLKOUT_D DDR Bank D Serial Control Data (Neg)
DDC_SCTRL_DP P26 O LVDS_25_O - DDC_DCLKOUT_D DDR Bank D Serial Control Data (Pos)
DDC_VERSION_0 F18 O LVCMOS25_F_12_O Hi = 1 - DLPC410 Firmware Rev Number bit 0
DDC_VERSION_1 G17 O LVCMOS25_F_12_O Hi = 1 - DLPC410 Firmware Rev Number bit 1
DDC_VERSION_2 H18 O LVCMOS25_F_12_O Hi = 1 - DLPC410 Firmware Rev Number bit 2
DDC_SPARE_1 AC21 - LVCMOS25_F_12_O Do not connect - - Not Used
DMD_A_RESET AD14 O LVCMOS25_F_12_O Connected in Reference Design to 36 Ω resistor with 27 pF cap to ground (signal name DMD_A_RESET_FILT after resistor - connects to DMD signal DMDRST) Lo - DMD Circuitry Reset (not data reset)
DMD_A_SCPEN AB14 O LVCMOS25_F_12_O Connected in Reference Design to 36 Ω resistor with 27 pF cap to ground (called DMD_A_SCPEN# in Reference Design- signal name DMD_A_SCPEN#_FILT after resistor - connects to DMD signal DMDSEL ) Lo - DMD SCP Output Enable
DMD_B_RESET AA12 O LVCMOS25_S_12_O Connected in Reference Design to 36 Ω resistor with 27 pF cap to ground (signal name DMD_B_RESET_FILT after resistor - NC after that point) - - Not Used
DMD_B_SCPEN AC14 O LVCMOS25_S_12_O Connected in Reference Design to 36 Ω resistor with 27 pF cap to ground (called DMD_B_SCPEN# in Reference Design - signal name DMD_B_SCPEN#_FILT after resistor - NC after that point ) - - Not Used
DMD_TYPE_0 AA17 O LVCMOS25_F_12_O Hi = 1 - DMD Attached Type bit 0
DMD_TYPE_1 AC16 O LVCMOS25_F_12_O Hi = 1 - DMD Attached Type bit 1
DMD_TYPE_2 AB17 O LVCMOS25_F_12_O Hi = 1 - DMD Attached Type bit 2
DMD_TYPE_3 AD15 O LVCMOS25_F_12_O Hi = 1 - DMD Attached Type bit 3
DONE_DDC K10 O - 4.7 kΩ pullup to 2.5V - connected to DLPR410 CE pin and LED D3 pin 3 (cathode) in series with 62 Ω resistor to 3.3 V Hi - DLPR410 Initialization Routine Complete
DVALID_A_DPN D20 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_A Bank A Valid Input Signal (Neg)
DVALID_A_DPP D21 I LVDS_25_I - DDC_DCLK_A Bank A Valid Input Signal (Pos)
DVALID_B_DPN C8 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_B Bank B Valid Input Signal (Neg)
DVALID_B_DPP D8 I LVDS_25_I - DDC_DCLK_B Bank B Valid Input Signal (Pos)
DVALID_C_DPN L19 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_C Bank C Valid Input Signal (Neg)
DVALID_C_DPP L20 I LVDS_25_I - DDC_DCLK_C Bank C Valid Input Signal (Pos)
DVALID_D_DPN L3 I LVDS_25 100 Ω across pair (not terminated in the DLPC410) - DDC_DCLK_D Bank D Valid Input Signal (Neg)
DVALID_D_DPP L4 I LVDS_25_I - DDC_DCLK_D Bank D Valid Input Signal (Pos)
DXN_0 R13 - NC TP17 in Reference Design - - Dedicated Xlilinx Temperature Diode (anode); Not Used in Reference Design
DXP_0 R14 - NC TP14 in Reference Design - - Dedicated Xlilinx Temperature Diode (cathode); Not Used in Reference Design
ECP2_FINISHED Y18 O LVCMOS25_F_12_O Connected to LED D3 pin 2 (anode) in series with 62 Ω resistor to 3.3 V Hi - DLPR410 Initialization Routine Complete
ECP2_M_TP0 AD11 - LVCMOS25_F_12_O Mictor J8 Pin 2 in Reference Design - - Not Used - do not connect
ECP2_M_TP1 AD10 - LVCMOS25_F_12_O Mictor J8 Pin 4 in Reference Design - - Reserved - do not connect
ECP2_M_TP2 AD8 - LVCMOS25_F_12_O Mictor J8 Pin 6 in Reference Design - - Reserved - do not connect
ECP2_M_TP3 AC8 O LVCMOS25_F_12_O Mictor J8 Pin 8 in Reference Design - - Buffered data clock - test point
ECP2_M_TP4 AC7 O LVCMOS25_F_12_O Mictor J8 Pin 10 in Reference Design - - Reserved - do not connect
ECP2_M_TP5 AC9 O LVCMOS25_F_12_O Mictor J8 Pin 12 in Reference Design Hi Reserved - do not connect
ECP2_M_TP6 AB9 O LVCMOS25_F_12_O Mictor J8 Pin 14 in Reference Design Hi Reserved - do not connect
ECP2_M_TP7 AA8 O LVCMOS25_F_12_O Mictor J8 Pin 16 in Reference Design Hi Reserved - do not connect
ECP2_M_TP8 AA9 O LVCMOS25_F_12_O Mictor J8 Pin 18 in Reference Design Hi Reserved - do not connect
ECP2_M_TP9 Y8 O LVCMOS25_F_12_O Mictor J8 Pin 20 in Reference Design - - Reserved - do not connect
ECP2_M_TP10 AB10 O LVCMOS25_F_12_O Mictor J8 Pin 22 in Reference Design Lo Reserved - do not connect
ECP2_M_TP11 AA10 O LVCMOS25_F_12_O Mictor J8 Pin 24 in Reference Design Hi Reserved - do not connect
ECP2_M_TP12 Y10 O LVCMOS25_F_12_O Mictor J8 Pin 26 in Reference Design Hi DMD A/B bus OK - test point
ECP2_M_TP13 AC11 O LVCMOS25_F_12_O Mictor J8 Pin 28 in Reference Design Hi DMD C/D bus OK - test point
ECP2_M_TP14 Y12 O LVCMOS25_F_12_O Mictor J8 Pin 30 in Reference Design Hi Reserved - do not connect
ECP2_M_TP15 Y11 O LVCMOS25_F_12_O Mictor J8 Pin 32 in Reference Design - Reserved - do not connect
ECP2_M_TP16 AB11 O LVCMOS25_F_12_O Mictor J8 Pin 34 in Reference Design Hi Reserved - do not connect
ECP2_M_TP17 H8 O LVCMOS25_F_12_O Mictor J8 Pin 36 in Reference Design Hi Reserved - do not connect
ECP2_M_TP18 H9 O LVCMOS25_F_12_O Mictor J8 Pin 38 in Reference Design Hi Reserved - do not connect
ECP2_M_TP19 F12 O LVCMOS25_F_12_O Mictor J8 Pin 37 in Reference Design - - Reserved - do not connect
ECP2_M_TP20 G11 O LVCMOS25_F_12_O Mictor J8 Pin 35 in Reference Design Hi Reserved - do not connect
ECP2_M_TP21 G12 O LVCMOS25_F_12_O Mictor J8 Pin 33 in Reference Design Hi Reserved - do not connect
ECP2_M_TP22 E11 O LVCMOS25_F_12_O Mictor J8 Pin 31 in Reference Design Hi Reserved - do not connect
ECP2_M_TP23 E10 O LVCMOS25_F_12_O Mictor J8 Pin 29 in Reference Design Hi Reserved - do not connect
ECP2_M_TP24 E8 O LVCMOS25_F_12_O Mictor J8 Pin 27 in Reference Design Hi Reserved - do not connect
ECP2_M_TP25 F10 O LVCMOS25_F_12_O Mictor J8 Pin 25 in Reference Design Hi Reserved - do not connect
ECP2_M_TP26 F9 O LVCMOS25_F_12_O Mictor J8 Pin 23 in Reference Design Hi Reserved - do not connect
ECP2_M_TP27 F8 O LVCMOS25_F_12_O Mictor J8 Pin 21 in Reference Design Hi Reserved - do not connect
ECP2_M_TP28 G10 O LVCMOS25_F_12_O Mictor J8 Pin 19 in Reference Design Hi Reserved - do not connect
ECP2_M_TP29 G9 O LVCMOS25_F_12_O Mictor J8 Pin 17 in Reference Design Hi Reserved - do not connect
ECP2_M_TP30 H11 O LVCMOS25_F_12_O Mictor J8 Pin 15 in Reference Design - - Reserved - do not connect
ECP2_M_TP31 H12 O LVCMOS25_F_12_O Mictor J8 Pin 13 in Reference Design - - Reserved - do not connect
GND A1, A6, A11, A16, A21, A26, AA1, AA11, AA21, AA26, AB8, AB18, AC5, AC15, AC25, AD2, AD12, AD22, AE4, AE9, AE14, AE19, AF1, AF6, AF11, AF16, AF21, AF26, B3, B8, B13, B18, C5, C15, C25, D2, D12, D22, E9, E19, F1, F6, F16, F26, G3, G13, G18, G23, H10, H20, J7, J9, J13, J15, J17, K4, K8, K12, K14, K16, K19, K24, L1, L9, L11, L13, L15, L17, L21, L26, M3, M8, M10, M12, M16, M18, N5, N9, N11, N15, N17, N25, P2, P7, P8, P10, P12, P16, P22, R9, R11, R15, R17, R19, T1, T6, T8, T10, T12, T14, T16, T26, U3, U9, U13, U15, U17, U18, U23, V8, V10, V14, V16, V20, W7, W9, W13, W15, W17, Y4, Y14, Y16, Y19, Y24 - GND - - Connect to Ground
HSWAPEN L18 - - 4.7 kΩ pullup to 2.5 V - - Xilinx Configuration
INIT_ACTIVE AA18 O LVCMOS25_F_12_O Hi - DLPC410 Initilization Routine Active
INTB_DDC J11 - - 4.7 kΩ pullup to 2.5 V connected to DLPR410 OE/RESET Hi - Xilinx Configuration
LOAD4 AB21 - LVCMOS25_F_12_I/O Previously DDC_SPARE_0, connected to Applications FPGA (U5) pin AD19 in Reference Design. Weak internal pull-up. Pull-up to logic '1' if LOAD4 is unused. - - LOAD4 mode enable
NS_FLIP F19 I LVCMOS25_S_12_I Hi - Top/Bottom image flip on DMD
PROGB_DDC J18 - 4.7 kΩ pullup to 2.5 V connected to DLPR410 CF Hi - Xilinx Configuration
PROM_CCK_DDC J10 I LVCMOS25_S_12 Connected to center of voltage divider (100/100 Ω) and through R53 to DLPR410 CLKOUT - PROM_CCK_DDC Configuration PROM Clock
PROM_D0_DDC K11 - - Connected to DLPR410 Data 0 (D0) - PROM_CCK_DDC Configuration PROM Data Out
PWR_FLOAT AC17 I LVCMOS25_S_12_I Connected to output of U22 NOR Gate (inputs V5_PWR_FLOAT and PWRGD) Hi - DMD Power Good indicator
RDWR_B P18 - - 1 kΩ pulldown to ground - - Xilinx Configuration
ROWAD_0 D14 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 0
ROWAD_1 D15 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 1
ROWAD_2 E15 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 2
ROWAD_3 F14 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 3
ROWAD_4 G14 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 4
ROWAD_5 E16 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 5
ROWAD_6 F15 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 6
ROWAD_7 G15 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 7
ROWAD_8 E17 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 8
ROWAD_9 F17 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 9
ROWAD_10 G16 I LVCMOS25_S_12_I Hi = 1 - DMD Row Address bit 10
ROWMD_0 H17 I LVCMOS25_S_12_I Hi = 1 - DMD Row Mode bit 0
ROWMD_1 H16 I LVCMOS25_S_12_I Hi = 1 - DMD Row Mode bit 1
RST_ACTIVE AB16 I LVCMOS25_F_12_O Hi = 1 - DMD Reset in Progress
RST2BLK E18 I LVCMOS25_S_12_I Hi = 1 - Dual Block Reset bit
RSVD_0 R18 - - Connect to Ground - - Not Used - must be tied to Ground
RSVD_1 T18 - - Connect to Ground - - Not Used - must be tied to Ground
SCPCLK AB15 LVCMOS25_F_12_O Connected to DLPA200 Number 1 and Number 2 SCPCLK and to R105 36 Ω filter resistor with 27 pF cap after - called DMD_A_SCPCLK_FILT after - connects to DMD SCPCLK (also connects to R97 filter resistor with 27 pF cap after - called DMD_B_SCPCLK_FILT but NC after) - SCPCLK SCP Clock
SCPDI AA15 I LVCMOS25_S_12_I 1 kΩ pullup to 2.5 V - connects to DLPA200 Number 1 and Number 2 SCPDO and to DMD SCPDO through flex A - on DMD board there is an LCR filter [2 x 100 pF caps, inductor and 34 Ω resistor] also connects to flex B but NC on other end. - SCPCLK SCP data input to DLPC410
SCPDO AA14 O LVCMOS25_F_12_O 1 kΩ pullup to 2.5 V - connects to DLPA200 Number 1 and Number 2 SCPDI and to R96 filter cap with 27 pF cap after - called DMD_A_FILTER - connect through flex A to DMD SCPDI - also connects to R71 36 Ω filter resistor with 27 pF cap to DMD_B_SCPDO_FILT but NC on other end. - SCPCLK SCP data output from DLPC410
STEPVCC Y13 - LVCMOS25_S_12_I 1 kΩ pulldown to ground - - Not Used
TCK_JTAG U11 - Connects to DLPC410, DLPR410, and JTAG header TCK (if user has JTAG they must build their chain accordingly) - TCK_JTAG JTAG Clock
TDO_DDC W10 - Connects to JTAG return TDO on JTAG header - TCK_JTAG JTAG data out of DLPC410
TDO_XCF16DDC V11 - Connects to DLPR410 TDO (DLPC410 internal signal TDI_0) - TCK_JTAG JTAG data out of DLPR410 to DLPC410
TMS_JTAG V12 - Connects to DLPC410, DLPR410, and JTAG header TMS Hi TCK_JTAG JTAG
VBATT_0 K18 - Connecteto 4.7 kΩ pullup to 2.5 V - - Not Used
VCCAUX J8, K17, L8, M17, N8, P17, R8, T17, U8, V17, W8, W16 POWER VCC_2P5V - - Aux Power
VCCINT H15, J12, J14, J16, K9, K13, K15, L10, L12, L14, L16, M9, M11, M15, N10, N12, N16, P9, P11, P15, R10, R12, R16, T9, T11, T13, T15, U10, U12, U14, U16, V9, V13, V15, W14, Y15 POWER VCC_1P0V - - Power
VCCO_0_1 Y9 POWER VCC_2P5V - - Power
VCCO_0_2 W12 POWER - - Power
VCCO_1_1 C10 POWER - - Power
VCCO_1_2 F11 POWER - - Power
VCCO_2_1 AA16 POWER - - Power
VCCO_2_2 AD17 POWER - - Power
VCCO_3_1 E14 POWER - - Power
VCCO_3_2 D17 POWER - - Power
VCCO_4_1 AC10 POWER - - Power
VCCO_4_2 AB13 POWER - - Power
VCCO_11_1 F21 POWER - - Power
VCCO_11_2 J22 POWER - - Power
VCCO_11_3 H25 POWER - - Power
VCCO_12_1 J2 POWER - - Power
VCCO_12_2 H5 POWER - - Power
VCCO_12_3 L6 POWER - - Power
VCCO_13_1 R24 POWER - - Power
VCCO_13_2 M23 POWER - - Power
VCCO_13_3 N20 POWER - - Power
VCCO_14_1 V5 POWER - - Power
VCCO_14_2 R4 POWER - - Power
VCCO_14_3 W2 POWER - - Power
VCCO_15_1 E24 POWER - - Power
VCCO_15_2 B23 POWER - - Power
VCCO_15_3 C20 POWER - - Power
VCCO_16_1 G8 POWER - - Power
VCCO_16_2 D7 POWER - - Power
VCCO_16_3 E4 POWER - - Power
VCCO_17_1 V25 POWER - - Power
VCCO_17_2 W22 POWER - - Power
VCCO_17_3 T21 POWER - - Power
VCCO_18_1 AD7 POWER - - Power
VCCO_18_2 AA6 POWER - - Power
VCCO_18_3 AB3 POWER VCC_2P5V - - Power
VLED0 AC18 O LVCMOS25_F_12_O Connects to LED D9 in series with 22.1 Ω resistor to 2.5 V Hi = On - Power Indicator LED Output
VLED1 AD18 O LVCMOS25_F_12_O Connects to LED D10 in series with 22.1 Ω resistor to 2.5 V Hi = On - Heartbeat Indicator LED Output
VN_0 P13 - - Connect to Ground - - Xilinx System Monitor (not used - must be connected to ground)
VP_0 N14 - - Connect to Ground - - Xilinx System Monitor (not used - must be connected to ground)
VREFN_0 N13 - LVCMOS25_S_12 Connect to Ground - - Xilinx System Monitor reference voltage (not used - must be connected to ground)
VREFP_0 P14 - LVCMOS25_S_12 Connect to Ground - - Xilinx System Monitor reference ground (not used - must be connected to ground)
WDT_ENBL AA13 I LVCMOS25_S_12_I Lo - DMD Mirror Clocking Pulse Watchdog Timer Enable
UNUSED AB23, AC20, AD9, AD16, AD20, AD21, AD23, AD24, AD25, AD26, AE7, AE8, AE10, AE11, AE12, AE13, AE15, AE16, AE17, AE18, AE20, AE21, AE22, AE23, AE24, AE25, AE26, AF7, AF8, AF9, AF10, AF12, AF13, AF14, AF15, AF17, AF18, AF19, AF20, AF22, AF23, AF24, AF25 NC No Connection (listed as Xilinx NC0 - NC42) - - Unused Pins