JAJSU19 April   2024 DLPC7530

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  DMD HSSI Electrical Characteristics
    8. 5.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 5.9  V-by-One Interface Electrical Characteristics
    10. 5.10 FPD-Link LVDS Electrical Characteristics
    11. 5.11 USB Electrical Characteristics
    12. 5.12 System Oscillator Timing Requirements
    13. 5.13 Power Supply and Reset Timing Requirements
    14. 5.14 DMD HSSI Timing Requirements
    15. 5.15 DMD Low-Speed LVDS Timing Requirements
    16. 5.16 V-by-One Interface General Timing Requirements
    17. 5.17 FPD-Link Interface General Timing Requirements
    18. 5.18 Parallel Interface General Timing Requirements
    19. 5.19 Source Frame Timing Requirements
    20. 5.20 Synchronous Serial Port Interface Timing Requirements
    21. 5.21 Controller and Target I2C Interface Timing Requirements
    22. 5.22 Programmable Output Clock Timing Requirements
    23. 5.23 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    24. 5.24 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    25. 5.25 Multi-Trace ETM Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 Processing Delays
      3. 6.3.3 Parallel Interface
      4. 6.3.4 FPD-Link Interface
      5. 6.3.5 V-by-One Interface
      6. 6.3.6 DMD (HSSI) Interface
      7. 6.3.7 Program Memory Flash Interface
      8. 6.3.8 GPIO Supported Functionality
      9. 6.3.9 Debug Support
    4. 6.4 Device Operational Modes
      1. 6.4.1 Standby Mode
      2. 6.4.2 Active Mode
        1. 6.4.2.1 Normal Configuration
        2. 6.4.2.2 Low Latency Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General Layout Guidelines
      2. 9.1.2  Power Supply Layout Guidelines
      3. 9.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4  Layout Guideline for DLPC7530 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5  V-by-One Interface Layout Considerations
      6. 9.1.6  FPD-Link Interface Layout Considerations
      7. 9.1.7  USB Interface Layout Considerations
      8. 9.1.8  DMD Interface Layout Considerations
      9. 9.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 9.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
      1. 10.6.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     92

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.4 3.3-V Power Supplies

The DLPC7530 can support a low cost power delivery system with a single 3.3-V power source derived from a switching regulator. To enable this approach, provide typical bulk (e.g. 10 µF, 22 µF) and high frequency (e.g. 0.1 µF) filtering for the main 3.3-V I/O power rail (VDD33). Ensure that the the high-frequency capacitors are evenly distributed amongst the power balls and that they are placed as close to the power balls as possible. Additional filtering must be provided for each of the uniquely defined 3.3-V power pins (e.g. VAD33_USB, VDD33_FPD). This is discussed further in Section 9.1 of the document.