DLPS253 September 2024 DLPC8445
PRODUCTION DATA
The DLPC8445 Controller DMD interface supports four High-Speed Serial Interface (HSSI) output-only interfaces for data transmission, a single-ended, low-speed LVDS output-only interface for command write transactions, as well as four low-speed single-ended input interfaces used for command read transactions. Each SubLVDS port supports full data-only inter-lane remapping within the port, but not between ports. When utilizing this feature, each unique data lane pair can only be mapped to one unique destination data lane pair, and intra-lane remapping (that is, swapping P with N) is not supported. In addition, the four HS data ports can also be swapped. The HS CLK pins are not interchangeable between ports and must be grouped with corresponding port data lanes. Lane and port remapping (specified in Flash) can help with board layout as needed. The number of HS ports and number of HS lanes per HS port required are based on DMD type and DMD display resolution. Table 6-9 shows some remapping examples for a two HS ports configuration with the same rules applying up to four HS ports. When all ports are used, they do not need the same pin mapping.
DLPC8445 Controller PINS - REMAPPING EXAMPLES TO DMD PINS | DMD PINS | |||
---|---|---|---|---|
BASELINE | FLIP HS0 180 No FLIP HS1 | SWAP HS0 PORT WITH HS1 PORT | SWAP HS0 PORT WITH HS1 PORT AND MIXED REMAPPING | |
DMD_HS0_CLK_P DMD_HS0_CLK_N | DMD_HS0_CLK_P DMD_HS0_CLK_N | DMD_HS1_CLK_P DMD_HS1_CLK_N | DMD_HS1_CLK_P DMD_HS1_CLK_N | DCLK_AP DCLK_AN |
DMD_HS0_WDATA0_P DMD_HS0_WDATA0_N | DMD_HS0_WDATA7_P DMD_HS0_WDATA7_N | DMD_HS1_WDATA0_P DMD_HS1_WDATA0_N | DMD_HS1_WDATA2_P DMD_HS1_WDATA2_N | D_AP(0) D_AN(0) |
DMD_HS0_WDATA1_P DMD_HS0_WDATA1_N | DMD_HS0_WDATA6_P DMD_HS0_WDATA6_N | DMD_HS1_WDATA1_P DMD_HS1_WDATA1_N | DMD_HS1_WDATA3_P DMD_HS1_WDATA3_N | D_AP(1) D_AN(1) |
DMD_HS0_WDATA2_P DMD_HS0_WDATA2_N | DMD_HS0_WDATA5_P DMD_HS0_WDATA5_N | DMD_HS1_WDATA2_P DMD_HS1_WDATA2_N | DMD_HS1_WDATA0_P DMD_HS1_WDATA0_N | D_AP(2) D_AN(2) |
DMD_HS0_WDATA3_P DMD_HS0_WDATA3_N | DMD_HS0_WDATA4_P DMD_HS0_WDATA4_N | DMD_HS1_WDATA3_P DMD_HS1_WDATA3_N | DMD_HS1_WDATA1_P DMD_HS1_WDATA1_N | D_AP(3) D_AN(3) |
DMD_HS0_WDATA4_P DMD_HS0_WDATA4_N | DMD_HS0_WDATA3_P DMD_HS0_WDATA3_N | DMD_HS1_WDATA4_P DMD_HS1_WDATA4_N | DMD_HS1_WDATA6_P DMD_HS1_WDATA6_N | D_AP(4) D_AN(4) |
DMD_HS0_WDATA5_P DMD_HS0_WDATA5_N | DMD_HS0_WDATA2_P DMD_HS0_WDATA2_N | DMD_HS1_WDATA5_P DMD_HS1_WDATA5_N | DMD_HS1_WDATA7_P DMD_HS1_WDATA7_N | D_AP(5) D_AN(5) |
DMD_HS0_WDATA6_P DMD_HS0_WDATA6_N | DMD_HS0_WDATA1_P DMD_HS0_WDATA1_N | DMD_HS1_WDATA6_P DMD_HS1_WDATA6_N | DMD_HS1_WDATA4_P DMD_HS1_WDATA4_N | D_AP(6) D_AN(6) |
DMD_HS0_WDATA7_P DMD_HS0_WDATA7_N | DMD_HS0_WDATA0_P DMD_HS0_WDATA0_N | DMD_HS1_WDATA7_P DMD_HS1_WDATA7_N | DMD_HS1_WDATA5_P DMD_HS1_WDATA5_N | D_AP(7) D_AN(7) |
DMD_HS1_CLK_P DMD_HS1_CLK_N | DMD_HS1_CLK_P DMD_HS1_CLK_N | DMD_HS0_CLK_P DMD_HS0_CLK_N | DMD_HS0_CLK_P DMD_HS0_CLK_N | DCLK_BP DCLK_BN |
DMD_HS1_WDATA0_P DMD_HS1_WDATA0_N | DMD_HS1_WDATA0_P DMD_HS1_WDATA0_N | DMD_HS0_WDATA0_P DMD_HS0_WDATA0_N | DMD_HS0_WDATA6_P DMD_HS0_WDATA6_N | D_BP(0) D_BN(0) |
DMD_HS1_WDATA1_P DMD_HS1_WDATA1_N | DMD_HS1_WDATA1_P DMD_HS1_WDATA1_N | DMD_HS0_WDATA1_P DMD_HS0_WDATA1_N | DMD_HS0_WDATA7_P DMD_HS0_WDATA7_N | D_BP(1) D_BN(1) |
DMD_HS1_WDATA2_P DMD_HS1_WDATA2_N | DMD_HS1_WDATA2_P DMD_HS1_WDATA2_N | DMD_HS0_WDATA2_P DMD_HS0_WDATA2_N | DMD_HS0_WDATA4_P DMD_HS0_WDATA4_N | D_BP(2) D_BN(2) |
DMD_HS1_WDATA3_P DMD_HS1_WDATA3_N | DMD_HS1_WDATA3_P DMD_HS1_WDATA3_N | DMD_HS0_WDATA3_P DMD_HS0_WDATA3_N | DMD_HS0_WDATA5_P DMD_HS0_WDATA5_N | D_BP(3) D_BN(3) |
DMD_HS1_WDATA4_P DMD_HS1_WDATA4_N | DMD_HS1_WDATA4_P DMD_HS1_WDATA4_N | DMD_HS0_WDATA4_P DMD_HS0_WDATA4_N | DMD_HS0_WDATA2_P DMD_HS0_WDATA2_N | D_BP(4) D_BN(4) |
DMD_HS1_WDATA5_P DMD_HS1_WDATA5_N | DMD_HS1_WDATA5_P DMD_HS1_WDATA5_N | DMD_HS0_WDATA5_P DMD_HS0_WDATA5_N | DMD_HS0_WDATA3_P DMD_HS0_WDATA3_N | D_BP(5) D_BN(5) |
DMD_HS1_WDATA6_P DMD_HS1_WDATA6_N | DMD_HS1_WDATA6_P DMD_HS1_WDATA6_N | DMD_HS0_WDATA6_P DMD_HS0_WDATA6_N | DMD_HS0_WDATA0_P DMD_HS0_WDATA0_N | D_BP(6) D_BN(6) |
DMD_HS1_WDATA7_P DMD_HS1_WDATA7_N | DMD_HS1_WDATA7_P DMD_HS1_WDATA7_N | DMD_HS0_WDATA7_P DMD_HS0_WDATA7_N | DMD_HS0_WDATA1_P DMD_HS0_WDATA1_N | D_BP(7) D_BN(7) |