DLPS253 September 2024 DLPC8445
PRODUCTION DATA
Although the DLPC8445 controller requires an array of power supply voltage pins there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC8445 controller (this remains true for both power-up and power-down scenarios). The controller requires no minimum delay time between powering up and powering down the individual supplies. Additional power sequencing rules may exist for devices that share the supplies with the DLPC8445 controller (such as the PMIC and DMD). These devices may force additional system power sequencing requirements. The DLPA3085 power-up sequence, the normal PARK power-down sequence, and the fast PARK power-down sequence of a typical DLPC8445 system are shown in the following figures.
t1: | Power applied to the system. All other voltage rails are derived from system input power. |
t2: | All supplies reach 95% of their specified nominal value. Note HOST_IRQ is an open drain output. |
t3: | Point where RESETZ is deasserted (goes high). This marks the beginning of auto-initialization. |
t4: | HOST_IRQ goes high to indicate initialization is complete and host communication may begin. |
(a): | PARKZ and PROJ_ON should be high prior to RESETZ release to support auto-initialization. |
(b): | tRAMP-UP-TOTAL, maximum time from 0.8V ramp start to all supplies stable. |
(c): | tREFCLK, minimum time reference clock must be stable before releasing RESETZ. |
(d): | I2C activity cannot start until HOST_IRQ goes high to indicate auto-initialization is completed. |
t1: | PROJ_ON goes low to begin the power down sequence. |
t2: | Controller completes DMD mirror parking sequence. |
t3: | RESETZ is asserted, HOST_IRQ goes high. |
t4: | All controller power supplies are turned off and discharged. |
t5: | System power can safely be removed. |
(a): | I2C activity after PROJ_ON is deasserted (goes low) is not supported. |
(b): | DMD mirror parking sequence begins when PROJ_ON is deasserted (going low). |
(c): | It is recommended that system input power be maintained within specifications well after PROJ_ON is deasserted (goes low) to allow time for DMD parking and supplies to fully power down. |
(d): | DLPA PMIC controls controller supply power down timing. |
t1: | A fault is detected (in this example the PMIC detects a UVLO condition) and PARKZ is asserted (goes low) to tell the controller to initiate a fast park of the DMD. |
t2: | The controller finishes the fast park procedure. |
t3: | RESETZ is asserted which puts the controller in a reset state which releases HOST_IRQ to a high. |
t4: | Eventually, all power supplies that were derived from SYSPWR collapse. |
(a): | All power supplies and the PLL_REFCLK must be held within specification for a minimum of 32 μs after PARKZ is asserted (goes low) to protect DMD from possible damage. |
(b): | The DMD has power sequencing requirements may impact the timing requirements of 1.8V supply, please refer to DMD data sheet for more information. |