DLPS253 September 2024 DLPC8445
PRODUCTION DATA
The DLPC8445 interfaces to a single external standard/dual/quad SPI serial Flash memory device for configuration and operational data. The 6-pin interface consists of an active low chip select signal, a clock signal, and four bi-directional data signals that can be used to support Standard/Dual/Quad SPI data I/O configurations as necessary during serial flash command execution. Table 6-10 shows a list of supported serial Flash devices that have been validated with the DLPC8445 controller.
DENSITY (Mbits) | VENDOR | PART NUMBER | PACKAGE SIZE |
---|---|---|---|
1.8V Compatible Devices | |||
8 | Macronix | MX25R8035FBHIH2 | WLCSP |
16 | Winbond | W25Q16JWBYIQ | WLCSP |
32 | Macronix | MX25U3232FBHI02 | WLCSP |
64 | Winbond | W25Q64JWBYIQ | WLCSP |
64 | Winbond | W25Q64JWSSIQ | WLCSP |
512 | GigaDevice | GD25LB512MEYIG | WSON |
3.3V Compatible Devices | |||
8 | Macronix | MX25R8035FBHIH2 | WLCSP |
The DLPC8445 can potentially support other standard/dual/quad SPI serial flash devices besides those shown in Table 6-10, provided that they have a similar feature set as shown in Table 6-11.
FEATURE | REQUIREMENT FOR COMPATIBILITY WITH DLPC8445 | COMMENTS |
---|---|---|
SPI data configuration (width) | Standard (SingleWire), Dual (Two Wire), Quad (Four Wire) | |
SPI clocking mode | SPI mode 0 | |
SPI clock frequency | up to 60MHz | |
Clock (↓) to Output Valid time | 6ns (max) | for example, tV or tCLQV |
Fast READ addressing | Auto-incrementing | |
Programming mode | Page mode | |
Page size | 256 Bytes | |
Sector (or Subsector) size | 4KB | Requirederase granularity |
Block structure | Uniform sector / Subsector | |
Block protection (BP) bits | Disabled (that is, ‘0’) by default | |
Status register bit(0) | Write In Progress (WIP) / BUSY | |
Status register bit(1) | Write enable latch (WEN) | |
Status register bits(4:2) | Block Protection bits (BP[2:0]) | |
Status register bit(7) | Status register write protect (SRWP) | |
Other Status Register bits | No specific status register bit assignment(s) required. “Other” status register bits often lack common/standard implementation details across vendors/devices. These “other” status register bits/signals can potentially be supported, although generally by the main application only (that is, particularly for devices not listed in Table 6-10). | for example, Quad Enable |
For compatibility with DLPC8445, serial flash devices must also support the following set of common commands.
SPI FLASH COMMAND | FIRST BYTE (OP-CODE) | SECOND BYTE | THIRD BYTE | FOURTH BYTE | FIFTH BYTE | SIXTH BYTE | NO. OF DUMMY CLOCKS | COMMENTS |
---|---|---|---|---|---|---|---|---|
Fast READ (1-1-1) | 0x0B | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0) | 8 | Variable data payload |
Dual READ (1-1-2) | 0x3B | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0) | 8 | Variable data payload |
2X READ (1-2-2) | 0xBB | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0) | 4 | Variable data payload |
Quad READ (1-1-4) | 0x6B | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0) | 8 | Variable data payload |
4X READ (1-4-4) | 0xEB | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0) | 6 | Variable data payload |
Read status | 0x05 | STATUS(0) | 0 | STATUS(0) Reg: bit 1 = WEL bit 0 = WIP/BUSY | ||||
Write status | 0x01 | STATUS(0) | 0 | |||||
Write Enable | 0x06 | 0 | ||||||
Write Disable | 0x04 | 0 | ||||||
Page program | 0x02 | ADDRS(0) | ADDRS(1) | ADDRS(2) | DATA(0) | DATA(1) | 0 | 256 byte data payload |
Sector/Subsector Erase (4KB) | 0x20 | ADDRS(0) | ADDRS(1) | ADDRS(2) | 0 | |||
Block Erase (64KB) | 0xD8 | ADDRS(0) | ADDRS(1) | ADDRS(2) | 0 | |||
Full Chip Erase | 0xC7 | 0 | ||||||
Software Reset Enable | 0x66 | 0 | ||||||
Software Reset | 0x99 | 0 | ||||||
Read Id | 0x9F | Data(0) | Data(1) | Data(2) | 0 | System only reads 1st three bytes. |
SPI data configuration details associated with the various READ commands in the common command set are summarized in Table 6-13.
READ COMMAND | SPI DATA I/O CONFIG FOR OPCODE (# Clocks) | SPI DATA I/O CONFIG FOR ADDRESS (# Clocks) | NUMBER OF DUMMY CLOCKS | SPI DATA I/O CONFIG FOR READ DATA (# Clocks) |
---|---|---|---|---|
Fast Read (1-1-1) | Standard (8) | Standard (8/byte) | 8 | Standard (8/byte) |
Dual Read (1-1-2) | Standard (8) | Standard (8/byte) | 8 | Dual (4/byte) |
2X Read (1-2-2) | Standard (8) | Dual (4/byte) | 4 | Dual (4/byte) |
Quad Read (1-1-4) | Standard (8) | Standard (8/byte) | 8 | Quad (2/byte) |
4X Read (1-4-4) | Standard (8) | Quad (2/byte) | 6 | Quad (2/byte) |
Host commands issued over the applicable host command interface (that is, I2C or SPI) can be used to program the serial flash device. The host can also specify target flash clock frequency and read command preferences in the flash table for DLPC8445 embedded software to use based on the system’s flash bandwidth requirements.