DLPS253 September   2024 DLPC8445

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     6
    2. 4.1  Initialization, Board Level Test, and Debug
    3. 4.2  V-by-One Interface Input Data and Control
    4. 4.3  FPD Link Port(s) Input Data and Control (Not Supported in DLPC8445)
    5. 4.4  DSI Input Data and Clock (Not Supported in DLPC8445)
    6. 4.5  DMD SubLVDS Interface
    7. 4.6  DMD Reset and Low Speed Interfaces
    8. 4.7  Flash Interface
    9. 4.8  Peripheral Interfaces
    10. 4.9  GPIO Peripheral Interface
    11. 4.10 Clock and PLL Support
    12. 4.11 Power and Ground
    13. 4.12 I/O Type Subscript Definition
    14. 4.13 Internal Pullup and Pulldown Characteristics
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2.     22
    3. 5.2  ESD Ratings
    4. 5.3  Recommended Operating Conditions
    5. 5.4  Thermal Information
    6. 5.5  Power Electrical Characteristics
    7. 5.6  Pin Electrical Characteristics
    8. 5.7  DMD SubLVDS Interface Electrical Characteristics
    9.     29
    10. 5.8  DMD Low Speed Interface Electrical Characteristics
    11.     31
    12. 5.9  V-by-One Interface Electrical Characteristics
    13. 5.10 USB Electrical Characteristics
    14.     34
    15. 5.11 System Oscillator Timing Requirements
    16.     36
    17. 5.12 Power Supply and Reset Timing Requirements
    18.     38
    19. 5.13 V-by-One Interface General Timing Requirements
    20.     40
    21. 5.14 Flash Interface Timing Requirements
    22.     42
    23. 5.15 Source Frame Timing Requirements
    24.     44
    25. 5.16 Synchronous Serial Port Interface Timing Requirements
    26.     46
    27. 5.17 I2C Interface Timing Requirements
    28. 5.18 Programmable Output Clock Timing Requirements
    29. 5.19 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    30.     50
    31. 5.20 DMD Low Speed Interface Timing Requirements
    32.     52
    33. 5.21 DMD SubLVDS Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 V-by-One Interface
      3. 6.3.3 DMD (SubLVDS) Interface
      4. 6.3.4 Serial Flash Interface
      5. 6.3.5 GPIO Supported Functionality
        1.       63
      6. 6.3.6 Debug Support
  8. 7 Power Supply Recommendations
    1. 7.1 System Power-Up and Power-Down Sequence
    2. 7.2 DMD Fast Park Control (PARKZ)
    3. 7.3 Power Supply Management
    4. 7.4 Hot Plug Usage
    5. 7.5 Power Supplies for Unused Input Source Interfaces
    6. 7.6 Power Supplies
      1. 7.6.1 Power Supplies DLPA3085
  9. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Layout Guideline for DLPC8445 Reference Clock
        1. 8.1.1.1 Recommended Crystal Oscillator Configuration
      2. 8.1.2 V-by-One Interface Layout Considerations
      3. 8.1.3 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 8.1.4 Power Supply Layout Guidelines
    2. 8.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Device Nomenclature
      1. 9.5.1 Device Markings
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
      1. 9.8.1 Video Timing Parameter Definitions
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • AMD|484
サーマルパッド・メカニカル・データ
発注情報

5.12 Power Supply and Reset Timing Requirements

Over operating free-air temperature range (unless otherwise noted)
PARAMETERMINMAXUNIT
tRAMP-UPPower supply ramp-up time.(1)Power supply ramp for each supply Ramp-up time: TOV × 10% to TOV × 90% TOV = Typical Operational Voltage10ms
18mv/µs
tRAMP-UP-TOTALTotal power supply ramp-up time.(1)Total time within which the 0.8V, 1.8V, and 3.3V supplies must complete their ramp-up. Ramp-up time: TOV × 10% to TOV × 90% TOV = Typical Operational Voltage100ms
tRAMP-DOWNPower supply ramp-down time.(1)Power supply ramp for each supply Ramp-down time: TOV × 90% to TOV × 10% TOV = Typical Operational Voltage0ms
tw1Pulse duration, in-active low, RESETZRESETZ inactive time 50% to 50% reference points (signal)100ms
tt1Transition time, RESETZ tt1 = tƒ1 and tr1Rise and Fall time for RESETZ(2) 20% to 80% reference points (signal25µs
tPROJ_ONPROJ_ON fall time delayPROJ_ON fall time delay to any power supply ≤ 80%10ms
tREFCLKATime to stable REFCLK(3)Time to stable REFLCKA before POSENSE1ms
(1) It is assumed that all 0.8V supplies come from the same source, although some will have additional filtering before entering the controller. As such, it is expected that these supplies will ramp together (aside from differences caused by filtering). This same expectation is true for the 1.8V and 3.3V supplies.
(2) As long as noise on this signal is below the hysteresis threshold.
(3) This delay requirement parameter is defined by design of REFCLK oscillator and defines the minimum time required for the internal oscillator to lock after the power supplys have ramped up and a stable external reference is provided and prior to release of RESETZ.