JAJSIP7D
September 2015 – September 2020
DLPC910
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Input LVDS Interface
7.3.2
Data Clock
7.3.3
Data Valid
7.3.4
Interface Training
7.3.5
Row and Block Interface
7.3.5.1
Row Mode
7.3.5.2
Block Mode
7.3.6
Control Interface
7.3.6.1
Complement Data
7.3.6.2
North South Flip
7.3.6.3
Watchdog
7.3.6.4
DMD Mirror Float
7.3.6.5
Load4
7.3.6.5.1
Load4 Row Addressing
7.3.6.5.2
Load4 Block Clears
7.3.7
Status Interface
7.3.7.1
ECP2 Finished
7.3.7.2
Initialization Active
7.3.7.3
Reset Active
7.3.7.4
DMD_TYPE
7.3.7.5
DDC_Version(2:0)
7.3.7.6
DMD_IRQ
7.3.7.7
LED Indicators
7.3.7.7.1
VLED0
7.3.7.7.2
VLED1
7.3.8
Reset and System Clock
7.3.8.1
Controller Reset
7.3.8.2
Main Oscillator Clock
7.3.9
I2C Interface
7.3.9.1
Configuration Pins
7.3.9.2
Communications Interface
7.3.9.2.1
Command Format
7.3.10
DMD Interface
7.3.10.1
DDC_DOUT
7.3.10.2
DDC_SCTRL
7.3.10.3
DDC_DCLKOUT
7.3.10.4
DMD Reset Interface
7.3.10.4.1
Mirror Reset Control
7.3.10.5
Enable and Interrupt Signals
7.3.10.6
Serial Control Port
7.3.11
Flash PROM Interface
7.3.11.1
JTAG Interface
7.3.11.2
PGM Interface
7.4
Device Functional Modes
7.4.1
DMD Row Operation
7.4.1.1
Data and Command Write Cycle
7.4.2
Block Mode Operation
7.4.3
Block Clear
7.4.4
Mirror Clocking Pulse
7.4.5
DMD Array Subset
7.4.6
Global Mirror Clocking Pulse Consideration
7.5
Register Map
7.5.1
Register Table Overview
7.5.1.1
DESTOP_INTERRUPT Register
7.5.1.2
MAIN_STATUS Register
7.5.1.3
DESTOP_CAL Register
7.5.1.4
DESTOP_DMD_ID_REG Register
7.5.1.5
DESTOP_CATBITS_REG Register
7.5.1.6
DESTOP_VERSION Register
7.5.1.7
DESTOP_RESET_REG Register
7.5.1.8
DESTOP_INFIFO_STATUS Register
7.5.1.9
DESTOP_BUS_SWAP Register
7.5.1.10
DESTOP_DMDCTRL Register
7.5.1.11
DESTOP_BIT_FLIP Register
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
High Speed Lithography Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
9
Power Supply Recommendations
9.1
Power Supply Distribution and Requirements
9.2
Power Down Requirements
10
Layout
10.1
Layout Guidelines
10.1.1
PCB Design Standards
10.1.2
Signal Layers
10.1.3
General PCB Routing
10.1.3.1
Trace Minimum Spacing
10.1.3.2
Trace Widths and Lengths
10.1.3.2.1
LVDS Output Bus Skew
10.1.3.3
Trace Impedance and Routing Priority
10.1.4
Power and Ground Planes
10.1.5
Power Vias
10.1.6
Decoupling
10.1.7
Flex Connector Plating
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Device Nomenclature
11.1.2
Device Markings
11.2
Documentation Support
11.2.1
Related Documentation
11.3
サポート・リソース
11.4
Trademarks
11.5
静電気放電に関する注意事項
11.6
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ZYR|676
MPBGAD2
サーマルパッド・メカニカル・データ
発注情報
jajsip7d_oa
7.3.8
Reset and System Clock