JAJSIP7D September   2015  – September 2020 DLPC910

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input LVDS Interface
      2. 7.3.2  Data Clock
      3. 7.3.3  Data Valid
      4. 7.3.4  Interface Training
      5. 7.3.5  Row and Block Interface
        1. 7.3.5.1 Row Mode
        2. 7.3.5.2 Block Mode
      6. 7.3.6  Control Interface
        1. 7.3.6.1 Complement Data
        2. 7.3.6.2 North South Flip
        3. 7.3.6.3 Watchdog
        4. 7.3.6.4 DMD Mirror Float
        5. 7.3.6.5 Load4
          1. 7.3.6.5.1 Load4 Row Addressing
          2. 7.3.6.5.2 Load4 Block Clears
      7. 7.3.7  Status Interface
        1. 7.3.7.1 ECP2 Finished
        2. 7.3.7.2 Initialization Active
        3. 7.3.7.3 Reset Active
        4. 7.3.7.4 DMD_TYPE
        5. 7.3.7.5 DDC_Version(2:0)
        6. 7.3.7.6 DMD_IRQ
        7. 7.3.7.7 LED Indicators
          1. 7.3.7.7.1 VLED0
          2. 7.3.7.7.2 VLED1
      8. 7.3.8  Reset and System Clock
        1. 7.3.8.1 Controller Reset
        2. 7.3.8.2 Main Oscillator Clock
      9. 7.3.9  I2C Interface
        1. 7.3.9.1 Configuration Pins
        2. 7.3.9.2 Communications Interface
          1. 7.3.9.2.1 Command Format
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 DDC_DOUT
        2. 7.3.10.2 DDC_SCTRL
        3. 7.3.10.3 DDC_DCLKOUT
        4. 7.3.10.4 DMD Reset Interface
          1. 7.3.10.4.1 Mirror Reset Control
        5. 7.3.10.5 Enable and Interrupt Signals
        6. 7.3.10.6 Serial Control Port
      11. 7.3.11 Flash PROM Interface
        1. 7.3.11.1 JTAG Interface
        2. 7.3.11.2 PGM Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 DMD Row Operation
        1. 7.4.1.1 Data and Command Write Cycle
      2. 7.4.2 Block Mode Operation
      3. 7.4.3 Block Clear
      4. 7.4.4 Mirror Clocking Pulse
      5. 7.4.5 DMD Array Subset
      6. 7.4.6 Global Mirror Clocking Pulse Consideration
    5. 7.5 Register Map
      1. 7.5.1 Register Table Overview
        1. 7.5.1.1  DESTOP_INTERRUPT Register
        2. 7.5.1.2  MAIN_STATUS Register
        3. 7.5.1.3  DESTOP_CAL Register
        4. 7.5.1.4  DESTOP_DMD_ID_REG Register
        5. 7.5.1.5  DESTOP_CATBITS_REG Register
        6. 7.5.1.6  DESTOP_VERSION Register
        7. 7.5.1.7  DESTOP_RESET_REG Register
        8. 7.5.1.8  DESTOP_INFIFO_STATUS Register
        9. 7.5.1.9  DESTOP_BUS_SWAP Register
        10. 7.5.1.10 DESTOP_DMDCTRL Register
        11. 7.5.1.11 DESTOP_BIT_FLIP Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Speed Lithography Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Distribution and Requirements
    2. 9.2 Power Down Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Design Standards
      2. 10.1.2 Signal Layers
      3. 10.1.3 General PCB Routing
        1. 10.1.3.1 Trace Minimum Spacing
        2. 10.1.3.2 Trace Widths and Lengths
          1. 10.1.3.2.1 LVDS Output Bus Skew
        3. 10.1.3.3 Trace Impedance and Routing Priority
      4. 10.1.4 Power and Ground Planes
      5. 10.1.5 Power Vias
      6. 10.1.6 Decoupling
      7. 10.1.7 Flex Connector Plating
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Pin Functions

PINI/O TYPEACTIVE
(HI OR LO)		CLOCK SYSTEMDESCRIPTION
NAMENO.
CTRL_RSTZF9LVCMOS25_ILo = 0-DLPC910 Reset.
DDC_I2C_ADDR_SELAA10LVCMOS33_IHi = 1-DLPC910 Secondary I2C Address Lo = 0x34, Hi = 0x36. Includes Internal pull-up.
DDC_I2C_SCLY8LVCMOS33_B--DLPC910 Secondary I2C Clock. Requires an external 1-kΩ pull-up resistor.
DDC_I2C_SDAAA8LVCMOS33_B-DDC_I2C_SCLDLPC910 Secondary I2C Data. Requires an external 1-kΩ pull-up resistor.
CLKIN_RE10LVCMOS25_I-Reference clock50-MHz Reference Clock
RESET_ADDR0AD18LVDCI_33_OHi-Connect to DMD RESET_ADDR0
RESET_ADDR1AC18LVDCI_33_OHi-Connect to DMD RESET_ADDR1
RESET_ADDR2AC17LVDCI_33_OHi-Connect to DMD RESET_ADDR2
RESET_ADDR3AC16LVDCI_33_OHi-Connect to DMD RESET_ADDR3
RESET_MODE0AC13LVDCI_33_OHi-Connect to DMD RESET_MODE0
RESET_MODE1AD13LVDCI_33_OHi-Connect to DMD RESET_MODE1
RESET_SEL0AD15LVDCI_33_OHi-Connect to DMD RESET_SEL0
RESET_SEL1AC14LVDCI_33_OHi-Connect to DMD RESET_SEL1
RESET_STROBEAD10LVDCI_33_OHi-Connect to DMD RESET_STROBE
RESET_OEZAD14LVDCI_33_OLo-Connect to DMD RESET_OEZ
RESET_IRQZAD8LVCMOS33_ILo-Connect to DMD RESET_IRQZ
RESET_RSTZAB10LVDCI_33_OLo-Connect to DMD PWRDNZ and RESETZ inputs
SCPCLKAC7LVDCI_33_O--Connect to DMD SCP_CLK
SCPDIAC8LVCMOS33_I-SCPCLKConnect to DMD SCP_DO
SCPDOAC9LVDCI_33_O-SCPCLKConnect to DMD SCP_DI
DMD_SCPENZAB9LVDCI_33_OLoSCPCLKConnect to DMD SCP_ENZ
DMD_TYPE_0G11LVCMOS25_OHi-Attached DMD Type bit 0
DMD_TYPE_1G12LVCMOS25_OHi-Attached DMD Type bit 1
DMD_TYPE_2H11LVCMOS25_OHi-Attached DMD Type bit 2
DMD_TYPE_3H12LVCMOS25_OHi-Attached DMD Type bit 3
BLKAD_0E12LVCMOS25_IHiDDC_DCLK_[A,B,C,D]Block Address bit 0
BLKAD_1D13LVCMOS25_IHiDDC_DCLK_[A,B,C,D]Block Address bit 1
BLKAD_2E13LVCMOS25_IHiDDC_DCLK_[A,B,C,D]Block Address bit 2
BLKAD_3F13LVCMOS25_IHiDDC_DCLK_[A,B,C,D]Block Address bit 3
BLKMD_0H13LVCMOS25_IHiDDC_DCLK_[A,B,C,D]Block Mode Bit 0
BLKMD_1H14LVCMOS25_IHiDDC_DCLK_[A,B,C,D]Block Mode Bit 1
ROWAD_0D14LVCMOS25_IHi-DMD Row Address bit 0
ROWAD_1D15LVCMOS25_IHi-DMD Row Address bit 1
ROWAD_2E15LVCMOS25_IHi-DMD Row Address bit 2
ROWAD_3F14LVCMOS25_IHi-DMD Row Address bit 3
ROWAD_4G14LVCMOS25_IHi-DMD Row Address bit 4
ROWAD_5E16LVCMOS25_IHi-DMD Row Address bit 5
ROWAD_6F15LVCMOS25_IHi-DMD Row Address bit 6
ROWAD_7G15LVCMOS25_IHi-DMD Row Address bit 7
ROWAD_8E17LVCMOS25_IHi-DMD Row Address bit 8
ROWAD_9F17LVCMOS25_IHi-DMD Row Address bit 9
ROWAD_10G16LVCMOS25_IHi-DMD Row Address bit 10
ROWMD_0H17LVCMOS25_IHi-DMD Row Mode bit 0
ROWMD_1H16LVCMOS25_IHi-DMD Row Mode bit 1
DDC_DCLK_A_DPNB21LVDS_25_NI--Input Bus A Clock. 100-Ω external LVDS termination required.
DDC_DCLK_A_DPPC21LVDS_25_PI--
DDC_DCLK_B_DPNA7LVDS_25_NI--Input Bus B Clock. 100-Ω external LVDS termination required.
DDC_DCLK_B_DPPB7LVDS_25_PI--
DDC_DCLK_C_DPNK20LVDS_25_NI--Input Bus C Clock. 100-Ω external LVDS termination required.
DDC_DCLK_C_DPPK21LVDS_25_PI--
DDC_DCLK_D_DPNL5LVDS_25_NI--Input Bus D Clock. 100-Ω external LVDS termination required.
DDC_DCLK_D_DPPK5LVDS_25_PI--
DDC_DCLKOUT_A_DPNN1LVDS_25_NO--Output Bus A Clock to DMD.
DDC_DCLKOUT_A_DPPM1LVDS_25_PO--
DDC_DCLKOUT_B_DPNY5LVDS_25_NO--Output Bus B Clock to DMD.
DDC_DCLKOUT_B_DPPY6LVDS_25_PO--
DDC_DCLKOUT_C_DPNAA22LVDS_25_NO--Output Bus C Clock to DMD.
DDC_DCLKOUT_C_DPPAB22LVDS_25_PO--
DDC_DCLKOUT_D_DPNM26LVDS_25_NO--Output Bus D Clock to DMD.
DDC_DCLKOUT_D_DPPM25LVDS_25_PO--
DDC_DIN_A0_DPNA15LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 0.
100-Ω external LVDS termination required.
DDC_DIN_A0_DPPA14LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A1_DPNB14LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 1.
100-Ω external LVDS termination required.
DDC_DIN_A1_DPPC14LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A2_DPNB16LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 2.
100-Ω external LVDS termination required.
DDC_DIN_A2_DPPB15LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A3_DPNC16LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 3.
100-Ω external LVDS termination required.
DDC_DIN_A3_DPPD16LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A4_DPNA17LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 4.
100-Ω external LVDS termination required.
DDC_DIN_A4_DPPB17LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A5_DPNC17LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 5.
100-Ω external LVDS termination required.
DDC_DIN_A5_DPPD18LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A6_DPNA19LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 6.
100-Ω external LVDS termination required.
DDC_DIN_A6_DPPA18LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A7_DPNC18LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 7.
100-Ω external LVDS termination required.
DDC_DIN_A7_DPPB19LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A8_DPND19LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 8.
100-Ω external LVDS termination required.
DDC_DIN_A8_DPPC19LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A9_DPNB20LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 9.
100-Ω external LVDS termination required.
DDC_DIN_A9_DPPA20LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A10_DPNA22LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 10.
100-Ω external LVDS termination required.
DDC_DIN_A10_DPPB22LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A11_DPNA24LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 11.
100-Ω external LVDS termination required.
DDC_DIN_A11_DPPA23LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A12_DPNC23LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 12.
100-Ω external LVDS termination required.
DDC_DIN_A12_DPPB24LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A13_DPNC24LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 13.
100-Ω external LVDS termination required.
DDC_DIN_A13_DPPD24LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A14_DPNA25LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 14.
100-Ω external LVDS termination required.
DDC_DIN_A14_DPPB25LVDS_25_PI-DDC_DCLK_A
DDC_DIN_A15_DPNC26LVDS_25_NI-DDC_DCLK_AInput Bus A Data bit 15.
100-Ω external LVDS termination required.
DDC_DIN_A15_DPPB26LVDS_25_PI-DDC_DCLK_A
DDC_DIN_B0_DPNA12LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 0.
100-Ω external LVDS termination required.
DDC_DIN_B0_DPPA13LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B1_DPNB12LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 1.
100-Ω external LVDS termination required.
DDC_DIN_B1_DPPC13LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B2_DPND10LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 2.
100-Ω external LVDS termination required.
DDC_DIN_B2_DPPD11LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B3_DPNC12LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 3.
100-Ω external LVDS termination required.
DDC_DIN_B3_DPPC11LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B4_DPNA10LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 4.
100-Ω external LVDS termination required.
DDC_DIN_B4_DPPB11LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B5_DPND9LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 5.
100-Ω external LVDS termination required.
DDC_DIN_B5_DPPC9LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B6_DPNB10LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 6.
100-Ω external LVDS termination required.
DDC_DIN_B6_DPPB9LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B7_DPNA8LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 7.
100-Ω external LVDS termination required.
DDC_DIN_B7_DPPA9LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B8_DPND6LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 8.
100-Ω external LVDS termination required.
DDC_DIN_B8_DPPD5LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B9_DPNC7LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 9.
100-Ω external LVDS termination required.
DDC_DIN_B9_DPPC6LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B10_DPNB6LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 10.
100-Ω external LVDS termination required.
DDC_DIN_B10_DPPB5LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B11_DPND4LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 11.
100-Ω external LVDS termination required.
DDC_DIN_B11_DPPD3LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B12_DPNB4LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 12.
100-Ω external LVDS termination required.
DDC_DIN_B12_DPPC4LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B13_DPNC3LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 13.
100-Ω external LVDS termination required.
DDC_DIN_B13_DPPC2LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B14_DPNA3LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 14.
100-Ω external LVDS termination required.
DDC_DIN_B14_DPPA2LVDS_25_PI-DDC_DCLK_B
DDC_DIN_B15_DPNB2LVDS_25_NI-DDC_DCLK_BInput Bus B Data bit 15.
100-Ω external LVDS termination required.
DDC_DIN_B15_DPPB1LVDS_25_PI-DDC_DCLK_B
DDC_DIN_C0_DPNE20LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 0.
100-Ω external LVDS termination required.
DDC_DIN_C0_DPPE21LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C1_DPNF20LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 1.
100-Ω external LVDS termination required.
DDC_DIN_C1_DPPG20LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C2_DPNH19LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 2.
100-Ω external LVDS termination required.
DDC_DIN_C2_DPPJ19LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C3_DPNE23LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 3.
100-Ω external LVDS termination required.
DDC_DIN_C3_DPPE22LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C4_DPNF23LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 4.
100-Ω external LVDS termination required.
DDC_DIN_C4_DPPF22LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C5_DPNG22LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 5.
100-Ω external LVDS termination required.
DDC_DIN_C5_DPPG21LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C6_DPNJ20LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 6.
100-Ω external LVDS termination required.
DDC_DIN_C6_DPPJ21LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C7_DPNH22LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 7.
100-Ω external LVDS termination required.
DDC_DIN_C7_DPPH21LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C8_DPNJ23LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 8.
100-Ω external LVDS termination required.
DDC_DIN_C8_DPPH23LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C9_DPNK22LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 9.
100-Ω external LVDS termination required.
DDC_DIN_C9_DPPK23LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C10_DPNM19LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 10.
100-Ω external LVDS termination required.
DDC_DIN_C10_DPPM20LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C11_DPNM21LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 11.
100-Ω external LVDS termination required.
DDC_DIN_C11_DPPM22LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C12_DPNN19LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 12.
100-Ω external LVDS termination required.
DDC_DIN_C12_DPPP19LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C13_DPNN21LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 13.
100-Ω external LVDS termination required.
DDC_DIN_C13_DPPN22LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C14_DPNP20LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 14.
100-Ω external LVDS termination required.
DDC_DIN_C14_DPPP21LVDS_25_PI-DDC_DCLK_C
DDC_DIN_C15_DPNN23LVDS_25_NI-DDC_DCLK_CInput Bus C Data bit 15.
100-Ω external LVDS termination required.
DDC_DIN_C15_DPPP23LVDS_25_PI-DDC_DCLK_C
DDC_DIN_D0_DPNT3LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 0.
100-Ω external LVDS termination required.
DDC_DIN_D0_DPPR3LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D1_DPNR5LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 1.
100-Ω external LVDS termination required.
DDC_DIN_D1_DPPR6LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D2_DPNR7LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 2.
100-Ω external LVDS termination required.
DDC_DIN_D2_DPPP6LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D3_DPNN3LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 3.
100-Ω external LVDS termination required.
DDC_DIN_D3_DPPP3LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D4_DPNP4LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 4.
100-Ω external LVDS termination required.
DDC_DIN_D4_DPPP5LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D5_DPNN6LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 5.
100-Ω external LVDS termination required.
DDC_DIN_D5_DPPN7LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D6_DPNN4LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 6.
100-Ω external LVDS termination required.
DDC_DIN_D6_DPPM4LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D7_DPNM7LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 7.
100-Ω external LVDS termination required.
DDC_DIN_D7_DPPL7LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D8_DPNK7LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 8.
100-Ω external LVDS termination required.
DDC_DIN_D8_DPPK6LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D9_DPNJ4LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 9.
100-Ω external LVDS termination required.
DDC_DIN_D9_DPPJ5LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D10_DPNH7LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 10.
100-Ω external LVDS termination required.
DDC_DIN_D10_DPPJ6LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D11_DPNG4LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 11.
100-Ω external LVDS termination required.
DDC_DIN_D11_DPPH4LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D12_DPNG5LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 12.
100-Ω external LVDS termination required.
DDC_DIN_D12_DPPH6LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D13_DPNG7LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 13.
100-Ω external LVDS termination required.
DDC_DIN_D13_DPPG6LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D14_DPNF4LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 14.
100-Ω external LVDS termination required.
DDC_DIN_D14_DPPF5LVDS_25_PI-DDC_DCLK_D
DDC_DIN_D15_DPNE5LVDS_25_NI-DDC_DCLK_DInput Bus D Data bit 15.
100-Ω external LVDS termination required.
DDC_DIN_D15_DPPE6LVDS_25_PI-DDC_DCLK_D
DDC_DOUT_A0_DPNAE2LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 0 to DMD.
DDC_DOUT_A0_DPPAF2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A1_DPNAD1LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 1 to DMD.
DDC_DOUT_A1_DPPAE1LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A2_DPNAC1LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 2 to DMD.
DDC_DOUT_A2_DPPAC2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A3_DPNAB1LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 3 to DMD.
DDC_DOUT_A3_DPPAB2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A4_DPNY2LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 4 to DMD.
DDC_DOUT_A4_DPPAA2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A5_DPNW1LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 5 to DMD.
DDC_DOUT_A5_DPPY1LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A6_DPNV1LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 6 to DMD.
DDC_DOUT_A6_DPPV2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A7_DPNU1LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 7 to DMD.
DDC_DOUT_A7_DPPU2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A8_DPNR2LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 8 to DMD.
DDC_DOUT_A8_DPPT2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A9_DPNN2LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 9 to DMD.
DDC_DOUT_A9_DPPM2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A10_DPNK1LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 10 to DMD.
DDC_DOUT_A10_DPPL2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A11_DPNK2LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 11 to DMD.
DDC_DOUT_A11_DPPK3LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A12_DPNJ3LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 12 to DMD.
DDC_DOUT_A12_DPPH3LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A13_DPNH2LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 13 to DMD.
DDC_DOUT_A13_DPPJ1LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A14_DPNH1LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 14 to DMD.
DDC_DOUT_A14_DPPG1LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_A15_DPNG2LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Data bit 15 to DMD.
DDC_DOUT_A15_DPPF2LVDS_25_PO-DDC_DCLKOUT_A
DDC_DOUT_B0_DPNAE5LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 0 to DMD.
DDC_DOUT_B0_DPPAE6LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B1_DPNAD3LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 1 to DMD.
DDC_DOUT_B1_DPPAD4LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B2_DPNAD5LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 2 to DMD.
DDC_DOUT_B2_DPPAD6LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B3_DPNAC3LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 3 to DMD.
DDC_DOUT_B3_DPPAC4LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B4_DPNAB5LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 4 to DMD.
DDC_DOUT_B4_DPPAB6LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B5_DPNAB7LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 5 to DMD.
DDC_DOUT_B5_DPPAC6LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B6_DPNAA5LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 6 to DMD.
DDC_DOUT_B6_DPPAA4LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B7_DPNAA7LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 7 to DMD.
DDC_DOUT_B7_DPPY7LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B8_DPNY3LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 8 to DMD.
DDC_DOUT_B8_DPPW3LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B9_DPNW4LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 9 to DMD.
DDC_DOUT_B9_DPPV4LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B10_DPNW6LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 10 to DMD.
DDC_DOUT_B10_DPPW5LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B11_DPNV7LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 11 to DMD.
DDC_DOUT_B11_DPPV6LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B12_DPNU4LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 12 to DMD.
DDC_DOUT_B12_DPPV3LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B13_DPNT4LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 13 to DMD.
DDC_DOUT_B13_DPPT5LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B14_DPNU6LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 14 to DMD.
DDC_DOUT_B14_DPPU5LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_B15_DPNU7LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Data bit 15 to DMD.
DDC_DOUT_B15_DPPT7LVDS_25_PO-DDC_DCLKOUT_B
DDC_DOUT_C0_DPNT22LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 0 to DMD.
DDC_DOUT_C0_DPPT23LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C1_DPNR20LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 1 to DMD.
DDC_DOUT_C1_DPPR21LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C2_DPNT19LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 2 to DMD.
DDC_DOUT_C2_DPPT20LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C3_DPNU21LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 3 to DMD.
DDC_DOUT_C3_DPPU22LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C4_DPNU20LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 4 to DMD.
DDC_DOUT_C4_DPPU19LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C5_DPNV23LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 5 to DMD.
DDC_DOUT_C5_DPPV24LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C6_DPNV22LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 6 to DMD.
DDC_DOUT_C6_DPPV21LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C7_DPNW19LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 7 to DMD.
DDC_DOUT_C7_DPPV19LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C8_DPNW23LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 8 to DMD.
DDC_DOUT_C8_DPPW24LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C9_DPNY22LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 9 to DMD.
DDC_DOUT_C9_DPPY23LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C10_DPNY20LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 10 to DMD.
DDC_DOUT_C10_DPPY21LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C11_DPNAA24LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 11 to DMD.
DDC_DOUT_C11_DPPAA23LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C12_DPNAA19LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 12 to DMD.
DDC_DOUT_C12_DPPAA20LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C13_DPNAC24LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 13 to DMD.
DDC_DOUT_C13_DPPAB24LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C14_DPNAC19LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 14 to DMD.
DDC_DOUT_C14_DPPAD19LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_C15_DPNAC22LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Data bit 15 to DMD.
DDC_DOUT_C15_DPPAC23LVDS_25_PO-DDC_DCLKOUT_C
DDC_DOUT_D0_DPNAB26LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 0 to DMD.
DDC_DOUT_D0_DPPAC26LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D1_DPNAA25LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 1 to DMD.
DDC_DOUT_D1_DPPAB25LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D2_DPNY26LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 2 to DMD.
DDC_DOUT_D2_DPPY25LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D3_DPNW26LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 3 to DMD.
DDC_DOUT_D3_DPPW25LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D4_DPNU26LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 4 to DMD.
DDC_DOUT_D4_DPPV26LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D5_DPNU25LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 5 to DMD.
DDC_DOUT_D5_DPPU24LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D6_DPNT25LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 6 to DMD.
DDC_DOUT_D6_DPPT24LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D7_DPNR26LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 7 to DMD.
DDC_DOUT_D7_DPPR25LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D8_DPNP24LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 8 to DMD.
DDC_DOUT_D8_DPPP25LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D9_DPNN24LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 9 to DMD.
DDC_DOUT_D9_DPPM24LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D10_DPNL25LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 10 to DMD.
DDC_DOUT_D10_DPPL24LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D11_DPNK26LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 11 to DMD.
DDC_DOUT_D11_DPPK25LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D12_DPNJ26LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 12 to DMD.
DDC_DOUT_D12_DPPJ25LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D13_DPNJ24LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 13 to DMD.
DDC_DOUT_D13_DPPH24LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D14_DPNH26LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 14 to DMD.
DDC_DOUT_D14_DPPG26LVDS_25_PO-DDC_DCLKOUT_D
DDC_DOUT_D15_DPNG25LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Data bit 15 to DMD.
DDC_DOUT_D15_DPPG24LVDS_25_PO-DDC_DCLKOUT_D
DDC_SCTRL_ANR1LVDS_25_NO-DDC_DCLKOUT_AOutput Bus A Serial Control to DMD.
DDC_SCTRL_APP1LVDS_25_PO-DDC_DCLKOUT_A
DDC_SCTRL_BNAA3LVDS_25_NO-DDC_DCLKOUT_BOutput Bus B Serial Control to DMD.
DDC_SCTRL_BPAB4LVDS_25_PO-DDC_DCLKOUT_B
DDC_SCTRL_CNW20LVDS_25_NO-DDC_DCLKOUT_COutput Bus C Serial Control to DMD.
DDC_SCTRL_CPW21LVDS_25_PO-DDC_DCLKOUT_C
DDC_SCTRL_DNN26LVDS_25_NO-DDC_DCLKOUT_DOutput Bus D Serial Control to DMD.
DDC_SCTRL_DPP26LVDS_25_PO-DDC_DCLKOUT_D
DVALID_A_DPND20LVDS_25_NI-DDC_DCLK_AInput Bus A Data Valid Signal.
100-Ω external LVDS termination required.
DVALID_A_DPPD21LVDS_25_PI-DDC_DCLK_A
DVALID_B_DPNC8LVDS_25_NI-DDC_DCLK_BInput Bus B Data Valid Signal.
100-Ω external LVDS termination required.
DVALID_B_DPPD8LVDS_25_PI-DDC_DCLK_B
DVALID_C_DPNL19LVDS_25_NI-DDC_DCLK_CInput Bus C Data Valid Signal.
100-Ω external LVDS termination required.
DVALID_C_DPPL20LVDS_25_PI-DDC_DCLK_C
DVALID_D_DPNL3LVDS_25_NI-DDC_DCLK_DInput Bus D Data Valid Signal.
100-Ω external LVDS termination required.
DVALID_D_DPPL4LVDS_25_PI-DDC_DCLK_D
DDC_VERSION_0F18LVCMOS25_OHi-DLPC910 Firmware Rev Number bit 0
DDC_VERSION_1G17LVCMOS25_OHi-DLPC910 Firmware Rev Number bit 1
DDC_VERSION_2H18LVCMOS25_OHi-DLPC910 Firmware Rev Number bit 2
SPEED_SEL_0H8LVCMOS25_IHi-SPEED_SEL[1:0]
= 00 400MHz
= 01 480MHz
= 10, 11 Reserved Includes internal pull-ups. SPEED_SEL[1:0] must be set to 00 when connecting the DLPC910 with a DLP6500.
SPEED_SEL_1H9LVCMOS25_IHi-
VSP_ENABLEE8LVCMOS25_IHi-Reserved. Do not connect. Includes internal pull-up.
ECP2_FINISHEDE25LVCMOS25_OHi-DLPR910 Initialization complete. Connected to LED.
VLED0AA17LVCMOS25_OHi = On-Power Indicator LED Output.
VLED1AB17LVCMOS25_OHi = On-Heartbeat Indicator LED Output.
WDT_ENBLZF25LVCMOS25_ILo-DMD Reset Pulse Watchdog Timer Enable
PWR_FLOATG9LVCMOS25_IHi-Park DMD mirrors.
NS_FLIPF19LVCMOS25_IHi-Top/Bottom image flip on DMD
COMP_DATAG19LVCMOS25_IHiDDC_DCLK_[A,B,C,D]Compliment Data (0 <--> 1)
INIT_ACTIVEE26LVCMOS25_OHi-DLPC910 Initialization Routine Active
RST_ACTIVEG10LVCMOS25_OHi-DMD Mirror Clocking Pulse in progress
RST2BLKZE18LVCMOS25_IHi-Dual and Quad Block control
TST_PT_0Y12LVCMOS33_O--No connect. For access to test point output route to test via.
TST_PT_1AA12LVCMOS33_O--No connect. For access to test point output route to test via.
TST_PT_2Y13LVCMOS33_O--No connect. For access to test point output route to test via.
TST_PT_3AA13LVCMOS33_O--No connect. For access to test point output route to test via.
TST_PT_4AA14LVCMOS33_O--No connect. For access to test point output route to test via.
TST_PT_5AB14LVCMOS33_O--No connect. For access to test point output route to test via.
TST_PT_6AA15LVCMOS33_O--No connect. For access to test point output route to test via.
TST_PT_7AB15LVCMOS33_O--No connect. For access to test point output route to test via.
TST_PT_8C1LVCMOS25_O--No connect. For access to test point output route to test via.
TST_PT_9D1LVCMOS25_O--No connect. For access to test point output route to test via.
TST_PT_10E1LVCMOS25_O--No connect. For access to test point output route to test via.
TST_PT_11E2LVCMOS25_O--No connect. For access to test point output route to test via.
TST_PT_12E3LVCMOS25_O--No connect. For access to test point output route to test via.
TST_PT_13F3LVCMOS25_O--No connect. For access to test point output route to test via.
TST_PT_14E7LVCMOS25_O--No connect. For access to test point output route to test via.
TST_PT_15F7LVCMOS25_O--No connect. For access to test point output route to test via.
DLPC_VRN_BANK4AB12DCI Reference Voltage--Requires an external 49.9-Ω pull-up resistor to 3.3 V.
DLPC_VRP_BANK4AC11DCI Reference Voltage--Requires an external 49.9-Ω pull-down resistor to GND.
LOAD4_ENZD25LVCMOS25_ILo-Signal enables the Load-4 functionality of the DMD. Includes internal pull-up.
DMD_IRQD26LVCMOS25_OHi-Signal indicates a DMD voltage is inactive. Includes internal pull-up
DLPC_VBATTK18LVCMOS33_I--DLPC910 VBATT reference. Connect to GND.
DLPC_DONEK10LVCOMS33_O--DLPC910 Initialization configuration complete. Connect to DLPR910 CEZ pin. Requires 4.7-kΩ pull-up to 3.3 V.
DLPC_HSWAPENL18LVCMOS33_I--DLPC910 Configuration. Requires 4.7-kΩ pull-up to 3.3 V.
DDC_M0W18LVCMOS33_I--DLPC910 Configuration. Connect to GND
DDC_M1Y17LVCMOS33_I--DLPC910 Configuration. Connect to GND
DDC_M2V18LVCMOS33_I--DLPC910 Configuration. Connect to GND
INTB_DDCJ11LVCMOS25_OHi-DLPC910 Configuration. Connect to DLPR910 OE/RESET. Requires 4.7-kΩ pull-up to 3.3 V.
PROGB_DDCJ18LVCMOS25_OHi-DLPC910 Configuration. Connect to DLPR910 CF. Requires 4.7-kΩ pull-up to 3.3 V.
PROM_CCK_DDCJ10LVCMOS25_O-PROM_CCK_DDCConfiguration PROM Clock. Connect to DLPR910 CLK. Connects to center of voltage divider (100/100-Ω 3.3 V and GND).
PROM_D0_DDCK11LVCMOS25_I-PROM_CCK_DDCConfiguration PROM Data in. Connected to DLPR910 Data 0 (D0)
DLPC_DOUTBUSYW11LVCMOS25_I--Configuration PROM Busy. Connect to test via for debug only.
RDWR_BP18LVCMOS25_I--DLPC910 Configuration. Requires 1-kΩ pull-down to ground.
TCK_JTAGU11LVCMOS33_I-TCK_JTAGJTAG Clock. Connects to DLPC910, DLPR910, and JTAG header TCK (if user has JTAG they must build their chain accordingly)
TDO_DDCW10LVCMOS33_O-TCK_JTAGJTAG Data out of DLPC910. Connects to JTAG return TDO on JTAG header
TDO_XCF16DDCV11LVCMOS33_I-TCK_JTAGJTAG Data out of DLPR910 to DLPC910. Connects to DLPR910 TDO (DLPC910 internal signal TDI_0)
TMS_JTAGV12LVCMOS33_IHiTCK_JTAGJTAG. Connects to DLPC910, DLPR910, and JTAG
header TMS
VCCAUXJ8, K17, L8, M17, N8, P17, R8, T17, U8, V17, W8, W16PWR--Aux Power. VCC_2P5V
VCCINTH15, J12, J14, J16, K9, K13, K15, L10, L12, L14, L16, M9, M11, M15, N10, N12, N16, P9, P11, P15, R10, R12, R16, T9, T11, T13, T15, U10, U12, U14, U16, V9, V13, V15, W14, Y15PWR--Power. VCC_1P0V
VCCO_0Y9, W12PWR--Power. VCC_3P3V
VCCO_2AA16, AD17PWR
VCCO_4AB13, AC10PWR--
VCCO_1C10, F11PWR--Power. VCC_2P5V
VCCO_3D17, E14PWR--
VCCO_11F21, H25, J22PWR--
VCCO_12H5, J2, L6PWR--
VCCO_13M23, N20, R24PWR--
VCCO_14R4, V5, W2PWR--
VCCO_15B23,C20, E24PWR--
VCCO_16D7, E4, G8PWR--
VCCO_17T21, V25, W22PWR--
VCCO_18AA6, AB3, AD7PWR--
VCCO_21AC20, AB23, AE24PWR--
GNDA1, A6, A11, A16, A21, A26, AA1, AA11, AA21, AA26, AB8, AB18, AC5, AC15, AC25, AD2, AD12, AD22, AE4, AE9, AE14, AE19, AF1, AF6, AF11, AF16, AF21, AF26, B3, B8, B13, B18, C5, C15, C25, D2, D12, D22, E9, E19, F1, F6, F16, F26, G3, G13, G18, G23, H10, H20, J7, J9, J13, J15, J17, K4, K8, K12, K14, K16, K19, K24, L1, L9, L11, L13, L15, L17, L21, L26, M3, M8, M10,GND--
M12, M16, M18, N5, N9, N11, N15, N17, N25, P2, P7, P8, P10, P12, P16, P22, R9, R11, R15, R17, R19, T1, T6, T8, T10, T12, T14, T16, T26, U3, U9, U13, U15, U17, U18, U23, V8, V10, V14, V16, V20, W7, W9, W13, W15,
W17, Y4, Y14, Y16, Y19, Y24, M13, M14, N13, N14, P13, P14, R13, R14, N18, R18, T18
RESERVED_AC12AC12LVCMOS33_O--Route to via for access to pin output.
RESERVED_AD11AD11LVCMOS33_O--Route to via for access to pin output.
RESERVED_AA9AA9LVCMOS33_I--Includes internal pull-up
RESERVED_Y10Y10LVCMOS33_I--Includes internal pull-up
RESERVED_Y11Y11LVCMOS33_I--Includes internal pull-up
RESERVED_AB11AB11LVCMOS33_I--Includes internal pull-up
RESERVED_F10F10LVCMOS33_I--Includes internal pull-up
RESERVED_F8F8LVCMOS33_I--Includes internal pull-up
UNUSEDA4, A5, AA18, AB16, AB19, AB20, AB21, AC21, AD9, AD16, AD20, AD21, AD23, AD24, AD25, AD26, AE3, AE7, AE8, AE10, AE11, AE12, AE13, AE15, AE16, AE17, AE18, AE20, AE21, AE22, AE23, AE25, AE26, AF3, AF4, AF5, AF7, AF8, AF9, AF10, AF12, AF13, AF14, AF15, AF17, AF18, AF19, AF20, AF22, AF23, AF24, AF25, C22, D23, E11, F12, F24, L22, L23, M5, M6, R22, R23, Y18NC--No Connection.
Unused Pins.