JAJSIP7D September 2015 – September 2020 DLPC910
PRODUCTION DATA
The MAIN_STATUS register is used for reading the status of the DLPC910. The register can be polled during operation to obtain the current state of the DLPC910.
ADDRESS | BITS | DESCRIPTION | RESET | TYPE |
---|---|---|---|---|
0x000C | 0 | DMD initialization in progress flag | 0x0 | R |
0 - No DMD initialization activity | ||||
1 - DMD initialization in progress | ||||
1 | DMD initialization in progress flag 1 | 0x0 | R | |
0 - No DMD stage 1 initialization activity | ||||
1 - DMD stage 1 initialization activity in progress | ||||
2 | DMD initialization in progress flag 2 | 0x0 | R | |
0 - No DMD stage 2 initialization activity | ||||
1 - DMD stage 2 initialization activity in progress | ||||
3 | DMD supports AB channels | 0x0 | R | |
0 - Operation of DMD AB buses not enabled | ||||
1 - Operation of DMD AB buses enabled | ||||
4 | DMD supports CD channels | 0x0 | R | |
0 - Operation of DMD CD buses not enabled | ||||
1 - Operation of DMD CD buses enabled | ||||
5 | Input interface calibration in progress | 0x0 | R | |
0 - Input interface calibration inactive | ||||
1 - Input interface calibration in progress | ||||
6 | DVALID alignment on interface A ok | 0x0 | R | |
0 - DVALID alignment invalid on channel A | ||||
1 - DVALID alignment correct on channel A | ||||
7 | DVALID alignment on interface B ok | 0x0 | R | |
0 - DVALID alignment invalid on channel B | ||||
1 - DVALID alignment correct on channel B | ||||
8 | DVALID alignment on interface C ok | 0x0 | R | |
0 - DVALID alignment invalid on channel C | ||||
1 - DVALID alignment correct on channel C | ||||
9 | DVALID alignment on interface D ok | 0x0 | R | |
0 - DVALID alignment invalid on channel D | ||||
1 - DVALID alignment correct on channel D | ||||
10 | System PLL locked flag | 0x0 | R | |
0 - PLL not locked | ||||
1 - PLL locked | ||||
11 | Reference PLL locked flag | 0x0 | R | |
0 - PLL not locked | ||||
1 - PLL locked | ||||
31:12 | UNUSED | 0x0 | R |