JAJST20A
March 2024 – September 2024
DLPC964
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Input High-Speed Serial (HSS) Interface
6.3.2
Block Interface
6.3.3
Control Interface
6.3.3.1
Watchdog
6.3.3.2
LOAD2
6.3.3.2.1
LOAD2 Row Addressing
6.3.3.2.2
LOAD2 Block Clears
6.3.3.3
Receiver Low Power Mode Enable
6.3.3.4
DMD High Speed Serial Interface (HSSI) Reset
6.3.3.5
DMD Power Enable
6.3.4
User K-Data Interface
6.3.5
Status Interface
6.3.5.1
INIT_DONE
6.3.5.2
MCP_ACTIVE
6.3.5.3
BLKLOADZ
6.3.5.4
High-Speed Serial Interface (HSSI) Bus Error
6.3.5.5
IRQZ
6.3.6
Reset, System Clock, and Power Good
6.3.6.1
Controller Reset
6.3.6.2
Main Oscillator Clock
6.3.6.3
DMD HSSI Bus Oscillator Clock
6.3.6.4
POWERGOOD and DMDPOWERGOOD
6.3.7
I2C Interface
6.3.7.1
Configuration Pins
6.3.7.2
Communications Interface
6.3.7.2.1
Command Format
6.3.8
DMD (HSSI) Interface
6.3.8.1
Park Control
6.3.8.2
Configurable HSSI Settings
6.3.9
Flash PROM Interface
6.3.9.1
JTAG Interface
6.4
Device Functional Modes
6.4.1
DLPC964 Aurora 64B/66B Input Data and Command Write Cycle
6.4.1.1
Block Mode Operation (Block Start with Block Control Word)
6.4.1.1.1
Block Clear and Block Set
6.4.1.1.2
Image Orientation—Block Load Increment / Decrement
6.4.1.1.3
Single Channel Mode
6.4.1.2
DMD Bit Plane Data Input (Quad Input Mode)
6.4.1.3
DMD Bit Plane Data Input (Single Input Mode)
6.4.1.4
Block Complete (DMDLOAD_REQ and BLKLOADZ)
6.4.2
DMD Row Operation
6.4.3
Block Load Address Select
6.4.4
Block Mode Select
6.4.5
Mirror Clocking Pulse (MCP)
6.5
Register Map
6.5.1
Register Table Overview
6.5.1.1
FPGA_INTERRUPT_STATUS Register
6.5.1.2
FPGA_INTERRUPT_ENABLE_CONTROL Register
6.5.1.3
FPGA_MAIN_STATUS Register
6.5.1.4
FPGA_VERSION Register
6.5.1.5
FPGA_MAIN_CTRL Register
6.5.1.6
SELF_TEST_REG Register
6.5.1.7
DMDIF_ERROR_STATUS_CLR Register
6.5.1.8
DMDIF_ERROR_STATUS Register
6.5.1.9
PRBS7_MACRO0_TEST_RESULT Register
6.5.1.10
PRBS7_MACRO1_TEST_RESULT Register
6.5.1.11
PRBS7_MACRO2_TEST_RESULT Register
6.5.1.12
PRBS7_MACRO3_TEST_RESULT Register
6.5.1.13
PRBS7_TEST_CONTROL Register
6.5.1.14
PRBS7_TEST_RUNSTATUS Register
6.5.1.15
LS_BUS_TEST_RESULT Register
6.5.1.16
DMD_TYPE Register
6.5.1.17
HSS_RESET Register
6.5.1.18
HSS_CHANNEL_STATUS Register
6.5.1.19
HSS_LANE_STATUS Register
6.5.1.20
HSS_CH0_SOFTERROR_COUNT Register
6.5.1.21
HSS_CH1_SOFTERROR_COUNT Register
6.5.1.22
HSS_CH2_SOFTERROR_COUNT Register
6.5.1.23
HSS_CH3_SOFTERROR_COUNT Register
6.5.1.24
HSS_SOFTERROR_COUNT_RESET Register
6.5.1.25
HSSI_Channel_0_DMD_Data_GT_Cell_Control Register
6.5.1.26
HSSI_Channel_0_DMD_Clock_GT_Cell_Control Register
6.5.1.27
HSSI_Channel_1_DMD_Data_GT_Cell_Control Register
6.5.1.28
HSSI_Channel_1_DMD_Clock_GT_Cell_Control Register
6.5.1.29
HSSI_Channel_2_DMD_Data_GT_Cell_Control Register
6.5.1.30
HSSI_Channel_2_DMD_Clock_GT_Cell_Control Register
6.5.1.31
HSSI_Channel_3_DMD_Data_GT_Cell_Control Register
6.5.1.32
HSSI_Channel_3_DMD_Clock_GT_Cell_Control Register
6.5.1.33
HSSI_DMD_Vcm_Value Register
6.5.1.34
TEST_DMD_ID Register
6.5.1.35
TEST_DMD_FUSE1 Register
6.5.1.36
TEST_DMD_FUSE2 Register
6.5.1.37
TEST_DMD_FUSE3 Register
6.5.1.38
TEST_DMD_FUSE4 Register
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
High Speed Direct Imaging Application
7.2.2
Design Requirements
7.2.3
Detailed Design Procedure
7.2.4
DMD Mirror Switching Performance Plots
7.3
Interfacing to DLPC964 Controller High Speed Serial (HSS) Aurora 64B/66B Inputs
7.3.1
Theory of Operation
7.3.1.1
Block Start with Block Control Word
7.3.1.2
Block Complete with DMDLOAD_REQ
7.3.1.3
DMDLOAD_REQ Setup Time Requirement
7.3.1.4
Single Channel Transfer Mode
7.3.1.5
DMD Block Array Data Mapping
7.4
Power Supply Recommendations
7.4.1
Power Supply Distribution and Requirements
7.4.2
Power Down Requirements
7.5
Layout
7.5.1
Layout Guidelines
7.5.1.1
PCB Design Standards
7.5.1.2
Signal Layers
7.5.1.3
General PCB Routing
7.5.1.3.1
Trace Minimum Spacing
7.5.1.3.2
Trace Length Matching
7.5.1.3.2.1
HSSI Output Bus Skew
7.5.1.3.2.2
Aurora 64B/66B Input Bus Skew
7.5.1.3.2.2.1
Other Timing Critical Signals
7.5.1.3.3
Trace Impedance and Routing Priority
7.5.2
Power and Ground Planes
7.5.3
Power Vias
7.5.4
Decoupling
7.6
Layout Example
8
Device and Documentation Support
8.1
Documentation Support
8.1.1
Related Documentation
8.2
ドキュメントの更新通知を受け取る方法
8.3
サポート・リソース
8.4
Trademarks
8.5
静電気放電に関する注意事項
8.6
用語集
9
Revision History
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
ZUM|1156
サーマルパッド・メカニカル・データ
発注情報
jajst20a_oa
6.5.1.38
TEST_DMD_FUSE4 Register
The TEST_DMD_FUSE4 Register contains the fuse settings for DMD fuse group 4.
Table 6-47 TEST_DMD_FUSE4 Register
Bit(s)
Description
Reset
Type
Notes
31:0
Fieldname:
TEST_DMD_FUSE4_FLD
0x0
r
DMD fuse group 4