The DMD HSSI bus reference clock inputs to
the DLPC964 controller, DMD_GTREFCLK_IN_A_N / DMD_GTREFCLK_IN_A_P, DMD_GTREFCLK_IN_B_N /
DMD_GTREFCLK_IN_B_P, DMD_GTREFCLK_IN_C_N / DMD_GTREFCLK_IN_C_P, and DMD_GTREFCLK_IN_D_N
/ DMD_GTREFCLK_IN_D_P, supplied from an oscillator must be 112.5MHz differential. This
clock should be valid prior to releasing SYS_ARSTZ.