JAJST20A March 2024 – September 2024 DLPC964
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The FPGA_MAIN_STATUS Register contains the status for the DLPC964 PLL Lock, DMD POWERGOOD, DMD Parked Status, and DMD High Speed Interface power status. This register is a read only register, and status bits can only be set/cleared by the DLPC964.
Bit(s) | Description | Reset | Type | Notes |
---|---|---|---|---|
0 | Fieldname: MAIN_STATUS_PLL_LOCKED_FLD | 0x0 | S | |
Read-only status | ||||
1: DLPC964 PLL locked | ||||
0: not locked | ||||
1 | Fieldname: MAIN_STATUS_DMDPWRGOOD_FLD | 0x0 | S | |
Read-only status | ||||
1: DMD power good from external regulator | ||||
0: DMD power not good from external regulator | ||||
2 | Fieldname: MAIN_STATUS_RSCDRC_DMDPARKED_FLD | 0x0 | S | |
Read-only status | ||||
1: DMD is parked | ||||
0: DMD is not parked | ||||
3 | Fieldname: MAIN_STATUS_HSIFPWRON_FLD | 0x0 | S | |
Read-only status. | ||||
1: DMD high speed interface power on | ||||
0: DMD high speed interface power off | ||||
31:4 | UNUSED | 0x0 |