JAJST20A March 2024 – September 2024 DLPC964
PRODUCTION DATA
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As shown in Figure 7-3, the data input to the DLPC964 controller through the AMD Aurora 64B/66B High Speed Serial (HSS) interface is arranged according to DMD array blocks. The DLP991U DMD has a total of sixteen DMD blocks, with each DMD block made up of an array of 4096 columns and 136 rows. A single row of 4096 DMD columns is then further divided into four segments of 1024 columns and independently mapped to the four HSS serial data input channels on the DLPC964. Each of the four independent HSS Aurora 64B/66B input channel cores (Channel 0, Channel 1, Channel 2, and Channel 3) control loading of 1024 columns and 136 rows, resulting in parallel loading of the full DMD block array of 4096 columns by 136 rows.