For correct power down operation of the DMD, the following power down procedure must be executed prior to an anticipated power removal:
- Assert the PARKZ signal low for a
minimum of 500μs to allow the DLPC964 to complete the power down procedure for
the attached DMD.
- During the 500μs the PARKZ signal
is held low, the DLPC964 will complete the power down procedure and deassert
DMD_PWREN low to shut down the DMD power supplies.
- Following the deassertion of
DMD_PWREN, power can be safely removed from the DLP chipset as shown in Figure 7-12.
In the event of an unanticipated power loss, the power management system must
detect the input power loss, assert the POWERGOOD signal to the DLPC964, and maintain
all operating power levels to the DLPC964 and the DMD for a minimum of 500μs to allow
the DLPC964 to complete the power down procedure for the attached DMD.
The proper sequence for parking the DMD and restarting the system
without removing power is shown in
Figure 7-13 and outlined in the
procedure below:
- Assert PARKZ low to park
DMD.
- Wait a minimum of 500μs for the
DLPC964 controller and DMD to complete DMD parking sequence.
- While PARKZ is still asserted
low, (keeping the DMD in parked state), assert SYS_ARSTZ low for minimum of 50ms
to reset the DLPC964 controller.
- Deassert SYS_ARSTZ to bring the
DLPC964 controller back to ready.
- Deassert PARKZ to unpark
DMD.
Table 7-6 Power Down Timing
Requirements
PARAMETER |
|
MIN |
MAX |
UNIT |
tpf |
PARKZ low time |
500 |
|
us |
tsa |
SYS_ARSTZ low time |
50 |
|
ms |
tps |
Minimum delay from SYS_ARSTZ active to PARKZ inactive |
0 |
|
ms |