JAJST20A March 2024 – September 2024 DLPC964
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The PCB layer design may vary depending on the system design. However, careful attention is required to meet design considerations. Table 7-13 shows a layer definition table and Figure 7-14 shows a PCB stack-up. The PCB stack-up uses Nelco N4000-13-SI as the dielectric material to improve the signal slew rate for better performance of the Aurora 64B/66B input interface and the HSSI DMD output interface.
LAYER | DESCRIPTION |
---|---|
Top | Top components. Low frequency signals routing, ground, voltage mini-planes |
2 | Ground |
3 | High speed signal layer |
4 | Ground |
5 | Split power plane |
6 | Split power plane |
7 | Ground |
8 | High speed signal layer |
9 | Ground |
Bottom | Discrete components. Low frequency signals routing, ground, voltage mini-planes |