JAJST20A March 2024 – September 2024 DLPC964
PRODUCTION DATA
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The DLPC964 controller provides an output signal to the Applications FPGA or customer front-end named BLKLOADZ that frames the loading of the most recently received block of data as it is being written to the DMD. This signal shall transition low when a DMD block load begins over the HSSI DMD interface and shall transition back high when the DMD block load is complete.