JAJST20A March 2024 – September 2024 DLPC964
PRODUCTION DATA
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The AMD Aurora 64B/66B high speed serial (HSS) interface is a generic data transport link without any concept of how the DMD block data structure must be arranged. To define the start of a DMD block, the APPS FPGA logic must send a block control word data packet through channel 0 of the Aurora 64B/66B User-K data port before DMD data transmission can begin.
Table 7-1 below contains detailed information regarding the Aurora User-K interface port. The User-K interface ports are used to implement application-specific control functions, are independent, and are higher priority than the data interface.
Name | Direction | Clock Domain | Description |
---|---|---|---|
USER_S_S_AXIS_TX | |||
s_axi_user_k_tx_tdata[0:(64n-1)] or s_axi_user_k_tx_tdata[(64n-1):0](1) | Input | user_clk | USER-K block data is 64-bit aligned. Signal Mapping per lane: |
Default: | |||
s_axi_user_k_tx_tdata={{4'h0,user_k_blk_no[0:3],user_k_data[55:0]}*n} | |||
Little endian format: | |||
s_axi_user_k_tx_tdata={{user_k_data[55:0],4'h0,user_k_blk_no[3:0]}*n} | |||
s_axi_user_k_tx_tvalid | Input | user_clk | Indicates valid User-K data on the s_axi_userk_tx_tdata port. |
s_axi_user_k_tx_tready | Output | user_clk | Indicates the Aurora 64B/66B core is ready to accept data on the s_axi_user_k_tx_tdata interface. |
USER_K_M_AXIS_RX | |||
m_axi_rx_user_k_tvalid | Output | user_clk | Indicates valid User-K data on the m_axi_user_k_tx_tdata port. |
m_axi_rx_user_k_tdata or m_axi_rx_user_k_tdata[(64n-1):0](1) | Output | user_clk | Received USER-K blocks from the Aurora 64B/66B lane are 64-bit aligned. |
Signal Mapping per lane: | |||
Default: | |||
m_axi_rx_user_k_tdata= {{4'h0,user_k_blk_no[0:3],user_k_data[55:0]}*n} | |||
Little endian format: | |||
m_axi_rx_user_k_tdata= {{user_k_data[55:0],4'h0,user_k_blk_no[3:0]}*n} |
As shown in Table 7-2 below, the HSS interface to the DLPC964 has four channels of User-K port interface exposed to the APPS FPGA user logics. Only Channel 0 is used to transmit the Block Control Word. Any Control Word packets sent over the User-K port of Channel 1, 2, and 3 are not used and are ignored by the DLPC964 Controller.
Signal Name | Signal Direction | DLPC964 Application Usage |
---|---|---|
gt0_s_axi_user_k_tx_tdata[191:0] | Input to Aurora Channel 0 | 192-bit block control word packet to be transmitted |
gt0_s_axi_user_k_tx_tvalid | Input to Aurora Channel 0 | User logic asserts this signal high to indicate to Aurora core the Block Control word is valid to transmit. Aurora cores ignore word if TVALID is not-asserted. |
gt0_s_axi_user_k_tx_tready | Output to Aurora Channel 0 | Aurora cores assert this signal high when the Block Control word is accepted. This signal is deasserted when words are ignored; that is, cores are not ready to accept input word. |
gt1_s_axi_user_k_tx_tdata[191:0] | Input to Aurora Channel 1 | Unused |
gt1_s_axi_user_k_tx_tvalid | Input to Aurora Channel 1 | Unused |
gt1_s_axi_user_k_tx_tready | Output to Aurora Channel 1 | Unused |
gt2_s_axi_user_k_tx_tdata[191:0] | Input to Aurora Channel 2 | Unused |
gt2_s_axi_user_k_tx_tvalid | Input to Aurora Channel 2 | Unused |
gt2_s_axi_user_k_tx_tready | Output to Aurora Channel 2 | Unused |
gt3_s_axi_user_k_tx_tdata[191:0] | Input to Aurora Channel 3 | Unused |
gt3_s_axi_user_k_tx_tvalid | Input to Aurora Channel 3 | Unused |
gt3_s_axi_user_k_tx_tready | Output to Aurora Channel 3 | Unused |
Table 7-3 describes the various fields within the 192-bit block control word. The block control word not only defines the start of a DMD block, but also contains instructions and information to guide the DLPC964 Controller in processing the received DMD Block Data from the APPS FPGA.
Field Position | Field Type | Field Description |
---|---|---|
gt0_s_axi_user_k_tx_tdata[7:0] | USER_K_BLOCK_NUMBER | Must set to zeros (0x00). Values other than 0x00 are invalid. DLPC964 controller ignores the entire 192-bit control word if this field is not set to 0x00. |
gt0_s_axi_user_k_tx_tdata[11:8] | BLOCK_ADDRESS | Indicates the address of the DMD block to which the DLPC964 applies the operation: 0000: DMD Block 0, 0001: DMD Block 1, 0010: DMD Block 2, …1110: DMD Block 14, 1111: DMD Block 15 |
gt0_s_axi_user_k_tx_tdata[15:7] | Reserved, Unused | |
gt0_s_axi_user_k_tx_tdata[24:16] | ROW_LENGTH | Number of DMD row to be loaded by DLPC964. DLP991U DMD has 136 rows per block, thus valid range is 1-136. All other values, including 0 are invalid. Set to 136 for full block operation. Set to 1–135 for partial block operation. |
NOTE: This field is only used if LOAD_TYPE = 000. | ||
gt0_s_axi_user_k_tx_tdata[34:32] | LOAD_TYPE | 000: Block Loading. The DLPC964 loads the user data to the DMD array defined by BLOCK_ADDRESS and ROW_LENGTH. |
001: Block Clear. The DLPC964 clears the DMD array to zeroes of the entire block defined by BLOCK_ADDRESS. | ||
010: Block Set. The DLPC964 sets the DMD array to ones of the entire block defined by BLOCK_ADDRESS. | ||
Other values: reserved, do not use. | ||
NOTE: when in 001 (Block Clear) or 010 (Block Set) operation, the ROW_LENGTH and NORTH_SOUTH_FLIP fields are ignored. Clear and Set operations affect the entire DMD Block array. Partial Block operation for Clear and Set operations is not supported. | ||
gt0_s_axi_user_k_tx_tdata[36] | NORTH_SOUTH_FLIP | Control the direction of data loading within a DMD Block. |
0: DLPC964 loads data starting and counting up from row 1. | ||
1: DLPC964 loads data starting and counting down from row 136 | ||
NOTE: This field is only used if LOAD_TYPE is 000. | ||
gt0_s_axi_user_k_tx_tdata[29:28] | DMD_SEGMENT | When SINGLE_CHANNEL_MODE = '1', DMD_SEGMENT is used to select which DMD segment is selected for the operation. |
00: Segment 0 | ||
01: Segment 1 | ||
10: Segment 2 | ||
11: Segment 3 | ||
NOTE: This field is ignored if SINGLE_CHANNEL_MODE = '0'. | ||
gt0_s_axi_user_k_tx_tdata[30] | SINGLE_CHANNEL_MODE | 1: Single Channel operation. DLPC964 Input Data for DMD is only received on Aurora Channel 0. |
0: Normal operation. DLPC964 Input Data for DMD is received on all four Aurora Channels. | ||
gt0_s_axi_user_k_tx_tdata[191:31] | Reserved, unused |
Figure 7-4 displays the transmission of the 192-bit block control word over the channel 0 User-K port at the start of an Aurora 64B/66B data block transfer. In this example, 136 rows of DMD block 1 are being loaded.