JAJSLL2B April   2021  – November 2021 DP83561-SP

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin States
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
      1. 6.6.1 Timing Requirement Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Engineering Model (Parts With /EM Suffix)
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Copper Ethernet
        1. 7.3.1.1 1000BASE-T
        2. 7.3.1.2 100BASE-TX
        3. 7.3.1.3 10BASE-Te
      2. 7.3.2 MAC Interfaces
        1. 7.3.2.1 Reduced GMII (RGMII)
          1. 7.3.2.1.1 RGMII-TX Requirements
          2. 7.3.2.1.2 RGMII-RX Requirements
          3. 7.3.2.1.3 1000-Mbps Mode Operation
          4. 7.3.2.1.4 1000-Mbps Mode Timing
          5. 7.3.2.1.5 10- and 100-Mbps Mode
        2. 7.3.2.2 Media Independent Interface (MII)
      3. 7.3.3 Auto-Negotiation
        1. 7.3.3.1 Speed and Duplex Selection - Priority Resolution
        2. 7.3.3.2 Master and Slave Resolution
        3. 7.3.3.3 Pause and Asymmetrical Pause Resolution
        4. 7.3.3.4 Next Page Support
        5. 7.3.3.5 Parallel Detection
        6. 7.3.3.6 Restart Auto-Negotiation
        7. 7.3.3.7 Enabling Auto-Negotiation Through Software
        8. 7.3.3.8 Auto-Negotiation Complete Time
        9. 7.3.3.9 Auto-MDIX Resolution
      4. 7.3.4 Speed Optimization
      5. 7.3.5 Radiation Performance
        1. 7.3.5.1 Total Ionizing Dose (TID)
        2. 7.3.5.2 Single-Event Effects (SEE)
        3. 7.3.5.3 Single Event Functional Interrupt (SEFI) Monitor Suite
          1. 7.3.5.3.1 PCS State Machine Monitors
          2. 7.3.5.3.2 Configuration Register Monitors
          3. 7.3.5.3.3 Temperature Monitor
          4. 7.3.5.3.4 PLL Lock Monitor
      6. 7.3.6 WoL (Wake-on-LAN) Packet Detection
        1. 7.3.6.1 Magic Packet Structure
        2. 7.3.6.2 Magic Packet Example
        3. 7.3.6.3 Wake-on-LAN Configuration and Status
      7. 7.3.7 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 7.3.7.1 SFD Latency Variation and Determinism
          1. 7.3.7.1.1 1000M SFD Variation in Master Mode
          2. 7.3.7.1.2 1000M SFD Variation in Slave Mode
          3. 7.3.7.1.3 100M SFD Variation
      8. 7.3.8 Cable Diagnostics
        1. 7.3.8.1 TDR
        2. 7.3.8.2 Fast Link Drop
        3. 7.3.8.3 Fast Link Detect
        4. 7.3.8.4 Energy Detect
        5. 7.3.8.5 IEEE 802.3 Test Modes
        6. 7.3.8.6 Jumbo Frames
      9. 7.3.9 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mirror Mode
      2. 7.4.2 Loopback Mode
        1. 7.4.2.1 Near-End Loopback
          1. 7.4.2.1.1 MII Loopback
          2. 7.4.2.1.2 PCS Loopback
          3. 7.4.2.1.3 Digital Loopback
          4. 7.4.2.1.4 Analog Loopback
          5. 7.4.2.1.5 External Loopback
          6. 7.4.2.1.6 Far-End (Reverse) Loopback
        2. 7.4.2.2 Loopback Availability Exception
      3. 7.4.3 Power-Saving Modes
        1. 7.4.3.1 IEEE Power Down
        2. 7.4.3.2 Deep Power-Down Mode
        3. 7.4.3.3 Active Sleep
        4. 7.4.3.4 Passive Sleep
    5. 7.5 Programming
      1. 7.5.1 Serial Management Interface
        1. 7.5.1.1 Extended Address Space Access
          1. 7.5.1.1.1 Write Address Operation
          2. 7.5.1.1.2 Read Address Operation
          3. 7.5.1.1.3 Write (No Post Increment) Operation
          4. 7.5.1.1.4 Read (No Post Increment) Operation
          5. 7.5.1.1.5 Write (Post Increment) Operation
          6. 7.5.1.1.6 Read (Post Increment) Operation
          7. 7.5.1.1.7 Example of Read Operation Using Indirect Register Access
          8. 7.5.1.1.8 Example of Write Operation Using Indirect Register Access
      2. 7.5.2 Interrupt
      3. 7.5.3 BIST Configuration
      4. 7.5.4 Strap Configuration
      5. 7.5.5 LED Configuration
      6. 7.5.6 LED Operation From 1.8-V I/O VDD Supply
      7. 7.5.7 Reset Operation
        1. 7.5.7.1 Hardware Reset
        2. 7.5.7.2 IEEE Software Reset
        3. 7.5.7.3 Global Software Reset
        4. 7.5.7.4 Global Software Restart
        5. 7.5.7.5 PCS Restart
    6. 7.6 Register Maps
      1. 7.6.1 DP83561SP Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clock Input
          1. 8.2.2.1.1 Crystal Recommendations
          2. 8.2.2.1.2 External Clock Source Recommendations
        2. 8.2.2.2 MAC Interface
          1. 8.2.2.2.1 RGMII Layout Guidelines
          2. 8.2.2.2.2 MII Layout Guidelines
        3. 8.2.2.3 Media Dependent Interface (MDI)
          1. 8.2.2.3.1 MDI Layout Guidelines
        4. 8.2.2.4 Magnetics Requirements
          1. 8.2.2.4.1 Magnetics Connection
  9. 9 Power Supply Recommendations
    1. 9.1 Two-Supply Configuration
    2. 9.2 Three-Supply Configuration
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Traces
      2. 10.1.2 Return Path
      3. 10.1.3 Transformer Layout
      4. 10.1.4 Metal Pour
      5. 10.1.5 PCB Layer Stacking
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.4 Strap Configuration

The DP83561-SP uses many of the functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap options are internally reloaded from the values sampled at power up or hard reset. The strap option pin assignments are defined below.

Configuration of the device may be done through strap pins or through the management register interface. A pullup resistor and/or a pulldown resistor of suggested values may be used to set the voltage ratio of the strap pin input and the supply to select one of the possible selected modes.

The MAC interface pins must support I/O voltages of 3.3 V, 2.5 V, and 1.8 V. As the strap inputs are implemented on these pins, the straps must also support operation at 3.3-V, 2.5-V, and 1.8-V supplies depending on what voltage was selected for I/O. RX_D0 and RX_D1 pins are 4 level strap pins. All other strap pins have two levels.

Figure 7-14 Strap Circuit
Table 7-7 4-Level Strap Resistor Ratio
MODETARGET VOLTAGEIDEAL RESISTORS
Vmin (V)Vtyp (V)Vmax (V)Rhi (kΩ)Rlo (kΩ)
0000.093 × VDDIOOPENOPEN
10.136 × VDDIO0.165 × VDDIO0.184 × VDDIO102.49
20.219 × VDDIO0.255 × VDDIO0.280 × VDDIO5.762.49
30.6 × VDDIO0.783 × VDDIO0.888 × VDDIO2.49OPEN
Table 7-8 2-Level Strap Resistor Ratio
MODETARGET VOLTAGEIDEAL RESISTORS
Vmin (V)Vtyp (V)Vmax (V)Rhi (kΩ)Rlo (kΩ)
000.18 x VDDIOOPEN2.49
10.5 x VDDIO0.88 x VDDIO2.49OPEN

Table 7-9 Strap Table

PIN NAME

STRAP NAME

PIN #

DEFAULT

FUNCTION

RX_D0

PHY_ADD[1:0]

44

0

PHY_ADD1

PHY_ADD0

MODE 0

0

0

MODE 1

0

1

MODE 2

1

0

MODE 3

1

1

RX_D1

PHY_ADD[3:2]

45

0

PHY_ADD3

PHY_ADD2

MODE 0

0

0

MODE 1

0

1

MODE 2

1

0

MODE 3

1

1

VDDIO_SEL_0

VDDIO_SEL_0

22

0

VDDIO level indication from system

VDDIO_SEL_1

VDDIO_SEL_0

Function

0

0

VDDIO = 3.3 V

VDDIO_SEL_1

VDDIO_SEL_1

21

0

0

1

Reserved

1

0

VDDIO = 2.5 V

1

1

VDDIO = 1.8 V

SUPPLYMODE_SEL

SUPPLYMODE_SEL

23

0

Triple or dual supply setting from system

0 = Dual supply mode (VDDA1P8 left floating)

1 = Triple supply mode (VDDA1P8 supplied by system)

CRS/GPIO_3

RGMII/MII_SEL

33

0

0 = RGMII

1 = MII

AUTO_RECOVER

AUTO_RECOVER

34

0

0 = DP83561-SP will take no automatic action based on SEFI. SEFI event interrupts will be generated normally.

1 = Configures the DP83561-SP to automatically apply RESET signal to PHY logic when a SEFI is detected. Default register values will be reloaded and pin options. SEFI event interrupts will be generated normally.

RX_DV/RX_CTRL

MIRROR_EN

49

0

0 = Port Mirroring Disabled

1 = Port Mirroring Enabled

SMI_DISABLE

SMI_DISABLE

50

0

0 = SMI(MDIO) writes are enabled.

1 = Station Management Interface (MDIO) writes are disabled.

LED_0

ANEG_DIS

63

0

0 = DP83561-SP will auto-negotiate link as defined in IEEE 802.3 Clause 28

1 = DP83561-SP set to forced link speed operation. Speed settings are controlled by ANEGSEL_0 and ANEGSEL_1 pin options.

LED_1

ANEGSEL_0

62

0

ANEG_DIS

ANEGSEL_1

ANEGSEL_0

Function

0

0

0

Auto-negotiation, 1000/100/10 advertised, Auto MDI-X

0

0

1

Auto-negotiation, 1000/100 advertised, Auto MDI-X

0

1

0

Auto-negotiation, 100/10 advertised,Auto-MDI-X

0

1

1

Reserved

LED_2/GPIO_0

ANEGSEL_1

61

0

1

0

0

Forced 1000M, master, MDI mode

1

0

1

Forced 1000M, slave, MDI mode

1

1

0

Forced 100M, full duplex, MDI mode

1

1

1

Forced 100M, full duplex, MDI-X mode