JAJSLL2B April   2021  – November 2021 DP83561-SP

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin States
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
      1. 6.6.1 Timing Requirement Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Engineering Model (Parts With /EM Suffix)
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Copper Ethernet
        1. 7.3.1.1 1000BASE-T
        2. 7.3.1.2 100BASE-TX
        3. 7.3.1.3 10BASE-Te
      2. 7.3.2 MAC Interfaces
        1. 7.3.2.1 Reduced GMII (RGMII)
          1. 7.3.2.1.1 RGMII-TX Requirements
          2. 7.3.2.1.2 RGMII-RX Requirements
          3. 7.3.2.1.3 1000-Mbps Mode Operation
          4. 7.3.2.1.4 1000-Mbps Mode Timing
          5. 7.3.2.1.5 10- and 100-Mbps Mode
        2. 7.3.2.2 Media Independent Interface (MII)
      3. 7.3.3 Auto-Negotiation
        1. 7.3.3.1 Speed and Duplex Selection - Priority Resolution
        2. 7.3.3.2 Master and Slave Resolution
        3. 7.3.3.3 Pause and Asymmetrical Pause Resolution
        4. 7.3.3.4 Next Page Support
        5. 7.3.3.5 Parallel Detection
        6. 7.3.3.6 Restart Auto-Negotiation
        7. 7.3.3.7 Enabling Auto-Negotiation Through Software
        8. 7.3.3.8 Auto-Negotiation Complete Time
        9. 7.3.3.9 Auto-MDIX Resolution
      4. 7.3.4 Speed Optimization
      5. 7.3.5 Radiation Performance
        1. 7.3.5.1 Total Ionizing Dose (TID)
        2. 7.3.5.2 Single-Event Effects (SEE)
        3. 7.3.5.3 Single Event Functional Interrupt (SEFI) Monitor Suite
          1. 7.3.5.3.1 PCS State Machine Monitors
          2. 7.3.5.3.2 Configuration Register Monitors
          3. 7.3.5.3.3 Temperature Monitor
          4. 7.3.5.3.4 PLL Lock Monitor
      6. 7.3.6 WoL (Wake-on-LAN) Packet Detection
        1. 7.3.6.1 Magic Packet Structure
        2. 7.3.6.2 Magic Packet Example
        3. 7.3.6.3 Wake-on-LAN Configuration and Status
      7. 7.3.7 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 7.3.7.1 SFD Latency Variation and Determinism
          1. 7.3.7.1.1 1000M SFD Variation in Master Mode
          2. 7.3.7.1.2 1000M SFD Variation in Slave Mode
          3. 7.3.7.1.3 100M SFD Variation
      8. 7.3.8 Cable Diagnostics
        1. 7.3.8.1 TDR
        2. 7.3.8.2 Fast Link Drop
        3. 7.3.8.3 Fast Link Detect
        4. 7.3.8.4 Energy Detect
        5. 7.3.8.5 IEEE 802.3 Test Modes
        6. 7.3.8.6 Jumbo Frames
      9. 7.3.9 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mirror Mode
      2. 7.4.2 Loopback Mode
        1. 7.4.2.1 Near-End Loopback
          1. 7.4.2.1.1 MII Loopback
          2. 7.4.2.1.2 PCS Loopback
          3. 7.4.2.1.3 Digital Loopback
          4. 7.4.2.1.4 Analog Loopback
          5. 7.4.2.1.5 External Loopback
          6. 7.4.2.1.6 Far-End (Reverse) Loopback
        2. 7.4.2.2 Loopback Availability Exception
      3. 7.4.3 Power-Saving Modes
        1. 7.4.3.1 IEEE Power Down
        2. 7.4.3.2 Deep Power-Down Mode
        3. 7.4.3.3 Active Sleep
        4. 7.4.3.4 Passive Sleep
    5. 7.5 Programming
      1. 7.5.1 Serial Management Interface
        1. 7.5.1.1 Extended Address Space Access
          1. 7.5.1.1.1 Write Address Operation
          2. 7.5.1.1.2 Read Address Operation
          3. 7.5.1.1.3 Write (No Post Increment) Operation
          4. 7.5.1.1.4 Read (No Post Increment) Operation
          5. 7.5.1.1.5 Write (Post Increment) Operation
          6. 7.5.1.1.6 Read (Post Increment) Operation
          7. 7.5.1.1.7 Example of Read Operation Using Indirect Register Access
          8. 7.5.1.1.8 Example of Write Operation Using Indirect Register Access
      2. 7.5.2 Interrupt
      3. 7.5.3 BIST Configuration
      4. 7.5.4 Strap Configuration
      5. 7.5.5 LED Configuration
      6. 7.5.6 LED Operation From 1.8-V I/O VDD Supply
      7. 7.5.7 Reset Operation
        1. 7.5.7.1 Hardware Reset
        2. 7.5.7.2 IEEE Software Reset
        3. 7.5.7.3 Global Software Reset
        4. 7.5.7.4 Global Software Restart
        5. 7.5.7.5 PCS Restart
    6. 7.6 Register Maps
      1. 7.6.1 DP83561SP Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clock Input
          1. 8.2.2.1.1 Crystal Recommendations
          2. 8.2.2.1.2 External Clock Source Recommendations
        2. 8.2.2.2 MAC Interface
          1. 8.2.2.2.1 RGMII Layout Guidelines
          2. 8.2.2.2.2 MII Layout Guidelines
        3. 8.2.2.3 Media Dependent Interface (MDI)
          1. 8.2.2.3.1 MDI Layout Guidelines
        4. 8.2.2.4 Magnetics Requirements
          1. 8.2.2.4.1 Magnetics Connection
  9. 9 Power Supply Recommendations
    1. 9.1 Two-Supply Configuration
    2. 9.2 Three-Supply Configuration
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Traces
      2. 10.1.2 Return Path
      3. 10.1.3 Transformer Layout
      4. 10.1.4 Metal Pour
      5. 10.1.5 PCB Layer Stacking
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

(1)
PARAMETER MIN NOM MAX UNIT
POWER-UP TIMING (2, 3 supply mode)
Supply ramp rate: For all supplies 0.5 100 ms
Supply delay offset between fully ramped (2V5, 1V1) and (VDDIO, 1V8) (3) 0 50 ms
T1 Last Supply power rail ramp  to RESET_N 200 ms
T2 Powerup to SMI ready: Post power-up stabilization time prior to MDC preamble for register access 200 ms
T3 Powerup to Strap latchin: Hardware configuration pins transition to output drivers 200 ms
Powerup to FLP 2000 ms
RESET TIMING
T1 Reset to SMI ready: Post reset stabilization time prior to MDC preamble for register access 30 us
T3 RESET PULSE Width: Miminum Reset pulse width to be able to reset 720 ns
T4 Reset to FLP 1750 ms
T4 Reset to 100M signaling (strapped mode) 194 us
T4 Reset to MAC clock  195 us
COPPER LINK TIMING
T1 Loss of Idles to Link LED low in Fast link down mode (100M) 10 us
Loss of Idles to Link LED low in Fast link down mode (1000M) 10 us
MII 100M TIMING
T1 TX_CLK High / Low Time 16 20 24 ns
T2 TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK 10 ns
T3 TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK 0 ns
T1 RX_CLK High / Low Time 16 20 24 ns
T2 RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising 10 30 ns
MII 10M Timings
10M TX_CLK High / Low Time 190 200 210 ns
TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK 25 ns
TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK 0 ns
RX_CLK High / Low Time 160 200 240 ns
RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising 100 300 ns
RGMII OUTPUT TIMING (1G)
TskewT Data to Clock Output Skew (Non-Delay Mode)(2) -600 625 ps
TskewT(Delay) Data to Clock Output Skew (Delay Mode : 2 ns default) 1.5 2 2.5 ns
TsetupT Data to Clock Output Setup ( Delay Mode) 1.2 ns
TholdT Data to Clock Output Hold ( Delay Mode) 1.2 ns
Tcyc Clock Cycle Duration 7.2 8 8.8 ns
Duty Cycle 45 50 58 %
Rise / Fall Time ( 20% to 80%) : with 5 pF Capacitive load 0.85 ns
RGMII INPUT TIMING (1G)
TsetupR TX data to clock input setup  1 ns
TholdR TX clock to data input hold 1 ns
DLL delay TX Input step 250 ps
SMI TIMING
T1 MDC to MDIO (Output) Delay Time (25 pF Load) 0 20 ns
T2 MDIO (Input) to MDC Setup Time 10 ns
T3 MDIO (Input) to MDC Hold Time 10 ns
T4 MDC Frequency (25 pF Load) 2.5 24 MHz
OUTPUT CLOCK TIMING (25MHz clockout)
Frequency (PPM) -100 100 -
Duty Cycle 40 60 %
Rise Time (5 pF Load) 5000 ps
Fall Time (5 pF Load) 5000 ps
Jitter (RMS) 40 ps
Jitter (Long Term) 375 ps
25MHz INPUT CLOCK tolerance
Frequency Tolerance -100 +100 ppm
Rise / Fall Time (10%-90%) 8 ns
Jitter Tolerance (Accumulated) 75 ps
Duty Cycle 40 60 %
TRANSMIT LATENCY TIMING
Copper RGMII to Cu (10M) : Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI 2560 ns
Copper MII to Cu (10M): Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI 525 ns
Copper RGMII to Cu (100M): Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI 169 ns
Copper MII to Cu (100M): Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI 64 ns
Copper RGMII to Cu (1G): Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI 106 ns
RECEIVE LATENCY TIMING
Copper Cu to RGMII (10M): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_CTRL 3000 ns
Copper Cu to MII (10M): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_DV 1650 ns
Copper Cu to RGMII (100M): SSD symbol on MDI to a) Rising edge of RX_DV  with assertion of RX_CTRL b) Rising edge of RX_DV  with assertion of RX_Dx 192 ns
Copper Cu to MII (100M): SSD symbol on MDI to a) Rising edge of RX_DV  with assertion of RX_CTRL b) Rising edge of RX_DV  with assertion of RX_Dx 220 ns
Copper Cu to RGMII (1G): SSD symbol on MDI to a) Rising edge of RX_DV  with assertion of RX_CTRL b) Rising edge of RX_DV  with assertion of RX_Dx 278 ns
(1) MII and RGMII Timing, Output Clock Timing, Input Clock jitter tolerance, Input Clock rise/fall time are characteristed by Design Simulation
(2) For RGMII interface, please refer to section "Reduced GMII" forRGMII timing and IBIS model based Signal Integrity simulation guidelines
(3) Ramp of all 4 supplies ( 2V5, 1V1, VDDIO, 1V8) together is preferred. VDDIO and 1V8 ( 3 supply config) can be delayed if needed. Refer to section "Power Supply recomendation"