SNOSAY8F September   2007  – April 2015 DP83640

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1  Pin Layout
    2. 3.2  Package Pin Assignments
    3. 3.3  Serial Management Interface (SMI)
    4. 3.4  MAC Data Interface
    5. 3.5  Clock Interface
    6. 3.6  LED Interface
    7. 3.7  IEEE 1588 Event/Trigger/Clock Interface
    8. 3.8  JTAG Interface
    9. 3.9  Reset and Power Down
    10. 3.10 Strap Options
    11. 3.11 10 Mb/s and 100 Mb/s PMD Interface
    12. 3.12 Power Supply Pins
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Specifications
    6. 4.6 AC Timing Requirements
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Media Configuration
      2. 5.3.2 Auto-Negotiation
        1. 5.3.2.1 Auto-Negotiation Pin Control
        2. 5.3.2.2 Auto-Negotiation Register Control
        3. 5.3.2.3 Auto-Negotiation Parallel Detection
        4. 5.3.2.4 Auto-Negotiation Restart
        5. 5.3.2.5 Enabling Auto-Negotiation Through Software
        6. 5.3.2.6 Auto-Negotiation Complete Time
      3. 5.3.3 Auto-MDIX
      4. 5.3.4 LED Interface
        1. 5.3.4.1 LEDs
        2. 5.3.4.2 LED Direct Control
      5. 5.3.5 Internal Loopback
      6. 5.3.6 Power Down/Interrupt
        1. 5.3.6.1 Power Down Control Mode
        2. 5.3.6.2 Interrupt Mechanisms
      7. 5.3.7 Energy Detect Mode
      8. 5.3.8 Link Diagnostic Capabilities
        1. 5.3.8.1 Linked Cable Status
          1. 5.3.8.1.1 Polarity Reversal
          2. 5.3.8.1.2 Cable Swap Indication
          3. 5.3.8.1.3 100-Mb Cable Length Estimation
          4. 5.3.8.1.4 Frequency Offset Relative to Link Partner
          5. 5.3.8.1.5 Cable Signal Quality Estimation
        2. 5.3.8.2 Link Quality Monitor
          1. 5.3.8.2.1 Link Quality Monitor Control and Status
          2. 5.3.8.2.2 Checking Current Parameter Values
          3. 5.3.8.2.3 Threshold Control
        3. 5.3.8.3 TDR Cable Diagnostics
        4. 5.3.8.4 TDR Pulse Generator
        5. 5.3.8.5 TDR Pulse Monitor
        6. 5.3.8.6 TDR Control Interface
        7. 5.3.8.7 TDR Results
      9. 5.3.9 BIST
    4. 5.4 Device Functional Modes
      1. 5.4.1  MAC Interface
      2. 5.4.2  MII Interface
        1. 5.4.2.1 Nibble-Wide MII Data Interface
        2. 5.4.2.2 Collision Detect
        3. 5.4.2.3 Carrier Sense
      3. 5.4.3  Reduced MII Interface
        1. 5.4.3.1 RMII Master Mode
        2. 5.4.3.2 RMII Slave Mode
      4. 5.4.4  Single Clock MII Mode
      5. 5.4.5  IEEE 802.3 MII Serial Management Interface
        1. 5.4.5.1 Serial Management Register Access
        2. 5.4.5.2 Serial Management Access Protocol
        3. 5.4.5.3 Serial Management Preamble Suppression
      6. 5.4.6  PHY Control Frames
      7. 5.4.7  PHY Status Frames
      8. 5.4.8  PHY Address
        1. 5.4.8.1 MII Isolate Mode
        2. 5.4.8.2 Broadcast Mode
      9. 5.4.9  Half Duplex vs. Full Duplex
      10. 5.4.10 Reset Operation
        1. 5.4.10.1 Hardware Reset
        2. 5.4.10.2 Full Software Reset
        3. 5.4.10.3 Soft Reset
        4. 5.4.10.4 PTP Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-Group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
        2. 5.5.1.2 100BASE-TX Receiver
          1. 5.5.1.2.1  Analog Front End
          2. 5.5.1.2.2  Digital Signal Processor
            1. 5.5.1.2.2.1 Base Line Wander Compensation
            2. 5.5.1.2.2.2 Digital Adaptive Equalization and Gain Control
          3. 5.5.1.2.3  Signal Detect
          4. 5.5.1.2.4  MLT-3 to Binary Decoder
          5. 5.5.1.2.5  Clock Recovery Module
          6. 5.5.1.2.6  NRZI to NRZ Decoder
          7. 5.5.1.2.7  Serial-to-Parallel
          8. 5.5.1.2.8  Descrambler
          9. 5.5.1.2.9  Code-Group Alignment
          10. 5.5.1.2.10 4B/5B Decoder
          11. 5.5.1.2.11 100BASE-TX Link Integrity Monitor
          12. 5.5.1.2.12 Bad SSD Detection
        3. 5.5.1.3 100BASE-FX Operation
          1. 5.5.1.3.1 100BASE-FX Transmit
          2. 5.5.1.3.2 100BASE-FX Receive
          3. 5.5.1.3.3 Far-End Fault
        4. 5.5.1.4 10BASE-T Transceiver Module
          1. 5.5.1.4.1  Operational Modes
          2. 5.5.1.4.2  Smart Squelch
          3. 5.5.1.4.3  Collision Detection and SQE
          4. 5.5.1.4.4  Carrier Sense
          5. 5.5.1.4.5  Normal Link Pulse Detection/Generation
          6. 5.5.1.4.6  Jabber Function
          7. 5.5.1.4.7  Automatic Link Polarity Detection and Correction
          8. 5.5.1.4.8  Transmit and Receive Filtering
          9. 5.5.1.4.9  Transmitter
          10. 5.5.1.4.10 Receiver
    6. 5.6 Memory
      1. 5.6.1 Register Block
        1. 5.6.1.1 Register Definition
          1. 5.6.1.1.1  Basic Mode Control Register (BMCR)
          2. 5.6.1.1.2  Basic Mode Status Register (BMSR)
          3. 5.6.1.1.3  PHY Identifier Register #1 (PHYIDR1)
          4. 5.6.1.1.4  PHY Identifier Register #2 (PHYIDR2)
          5. 5.6.1.1.5  Auto-Negotiation Advertisement Register (ANAR)
          6. 5.6.1.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
          7. 5.6.1.1.7  Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
          8. 5.6.1.1.8  Auto-Negotiate Expansion Register (ANER)
          9. 5.6.1.1.9  Auto-Negotiation Next Page Transmit Register (ANNPTR)
          10. 5.6.1.1.10 PHY Status Register (PHYSTS)
          11. 5.6.1.1.11 MII Interrupt Control Register (MICR)
          12. 5.6.1.1.12 MII Interrupt Status and Event Control Register (MISR)
          13. 5.6.1.1.13 Page Select Register (PAGESEL)
        2. 5.6.1.2 Extended Registers - Page 0
          1. 5.6.1.2.1  False Carrier Sense Counter Register (FCSCR)
          2. 5.6.1.2.2  Receiver Error Counter Register (RECR)
          3. 5.6.1.2.3  100 Mb/s PCS Configuration and Status Register (PCSR)
          4. 5.6.1.2.4  RMII and Bypass Register (RBR)
          5. 5.6.1.2.5  LED Direct Control Register (LEDCR)
          6. 5.6.1.2.6  PHY Control Register (PHYCR)
          7. 5.6.1.2.7  10Base-T Status/Control Register (10BTSCR)
          8. 5.6.1.2.8  CD Test and BIST Extensions Register (CDCTRL1)
          9. 5.6.1.2.9  PHY Control Register 2 (PHYCR2)
          10. 5.6.1.2.10 Energy Detect Control (EDCR)
          11. 5.6.1.2.11 PHY Control Frames Configuration Register (PCFCR)
        3. 5.6.1.3 Test Registers - Page 1
          1. 5.6.1.3.1 Signal Detect Configuration (SD_CNFG), Page 1
        4. 5.6.1.4 Link Diagnostics Registers - Page 2
          1. 5.6.1.4.1  100 Mb Length Detect Register (LEN100_DET), Page 2
          2. 5.6.1.4.2  100 Mb Frequency Offset Indication Register (FREQ100), Page 2
          3. 5.6.1.4.3  TDR Control Register (TDR_CTRL), Page 2
          4. 5.6.1.4.4  TDR Window Register (TDR_WIN), Page 2
          5. 5.6.1.4.5  TDR Peak Register (TDR_PEAK), Page 2
          6. 5.6.1.4.6  TDR Threshold Register (TDR_THR), Page 2
          7. 5.6.1.4.7  Variance Control Register (VAR_CTRL), Page 2
          8. 5.6.1.4.8  Variance Data Register (VAR_DATA), Page 2
          9. 5.6.1.4.9  Link Quality Monitor Register (LQMR), Page 2
          10. 5.6.1.4.10 Link Quality Data Register (LQDR), Page 2
          11. 5.6.1.4.11 Link Quality Monitor Register 2 (LQMR2), Page 2
        5. 5.6.1.5 PTP 1588 Base Registers - Page 4
          1. 5.6.1.5.1  PTP Control Register (PTP_CTL), Page 4
          2. 5.6.1.5.2  PTP Time Data Register (PTP_TDR), Page 4
          3. 5.6.1.5.3  PTP Status Register (PTP_STS), Page 4
          4. 5.6.1.5.4  PTP Trigger Status Register (PTP_TSTS), Page 4
          5. 5.6.1.5.5  PTP Rate Low Register (PTP_RATEL), Page 4
          6. 5.6.1.5.6  PTP Rate High Register (PTP_RATEH), Page 4
          7. 5.6.1.5.7  PTP Read Checksum (PTP_RDCKSUM), Page 4
          8. 5.6.1.5.8  PTP Write Checksum (PTP_WRCKSUM), Page 4
          9. 5.6.1.5.9  PTP Transmit Timestamp Register (PTP_TXTS), Page 4
          10. 5.6.1.5.10 PTP Receive Timestamp Register (PTP_RXTS), Page 4
          11. 5.6.1.5.11 PTP Event Status Register (PTP_ESTS), Page 4
          12. 5.6.1.5.12 PTP Event Data Register (PTP_EDATA), Page 4
        6. 5.6.1.6 PTP 1588 Configuration Registers - Page 5
          1. 5.6.1.6.1  PTP Trigger Configuration Register (PTP_TRIG), Page 5
          2. 5.6.1.6.2  PTP Event Configuration Register (PTP_EVNT), Page 5
          3. 5.6.1.6.3  PTP Transmit Configuration Register 0 (PTP_TXCFG0), Page 5
          4. 5.6.1.6.4  PTP Transmit Configuration Register 1 (PTP_TXCFG1), Page 5
          5. 5.6.1.6.5  PHY Status Frame Configuration Register 0 (PSF_CFG0), Page 5
          6. 5.6.1.6.6  PTP Receive Configuration Register 0 (PTP_RXCFG0), Page 5,
          7. 5.6.1.6.7  PTP Receive Configuration Register 1 (PTP_RXCFG1), Page 5
          8. 5.6.1.6.8  PTP Receive Configuration Register 2 (PTP_RXCFG2), Page 5
          9. 5.6.1.6.9  PTP Receive Configuration Register 3 (PTP_RXCFG3), Page 5
          10. 5.6.1.6.10 PTP Receive Configuration Register 4 (PTP_RXCFG4), Page 5
          11. 5.6.1.6.11 PTP Temporary Rate Duration Low Register (PTP_TRDL), Page 5
          12. 5.6.1.6.12 PTP Temporary Rate Duration High Register (PTP_TRDH), Page 5
        7. 5.6.1.7 PTP 1588 Configuration Registers - Page 6
          1. 5.6.1.7.1  PTP Clock Output Control Register (PTP_COC), Page 6
          2. 5.6.1.7.2  PHY Status Frame Configuration Register 1 (PSF_CFG1), Page 6
          3. 5.6.1.7.3  PHY Status Frame Configuration Register 2 (PSF_CFG2), Page 6
          4. 5.6.1.7.4  PHY Status Frame Configuration Register 3 (PSF_CFG3), Page 6
          5. 5.6.1.7.5  PHY Status Frame Configuration Register 4 (PSF_CFG4), Page 6
          6. 5.6.1.7.6  PTP SFD Configuration Register (PTP_SFDCFG), Page 6
          7. 5.6.1.7.7  PTP Interrupt Control Register (PTP_INTCTL), Page 6
          8. 5.6.1.7.8  PTP Clock Source Register (PTP_CLKSRC), Page 6
          9. 5.6.1.7.9  PTP Ethernet Type Register (PTP_ETR), Page 6
          10. 5.6.1.7.10 PTP Offset Register (PTP_OFF), Page 6
          11. 5.6.1.7.11 PTP GPIO Monitor Register (PTP_GPIOMON), Page 6
          12. 5.6.1.7.12 PTP Receive Hash Register (PTP_RXHASH), Page 6
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Key IEEE 1588 Features
        1. 6.1.1.1 IEEE 1588 Synchronized Clock
          1. 6.1.1.1.1 IEEE 1588 Clock Output
          2. 6.1.1.1.2 IEEE 1588 Clock Input
        2. 6.1.1.2 Packet Timestamps
          1. 6.1.1.2.1 IEEE 1588 Transmit Packet Parser and Timestamp
            1. 6.1.1.2.1.1 One-Step Operation
          2. 6.1.1.2.2 IEEE 1588 Receive Packet Parser and Timestamp
            1. 6.1.1.2.2.1 Receive Timestamp Insertion
          3. 6.1.1.2.3 NTP Packet Timestamp
        3. 6.1.1.3 Event Triggering and Timestamping
          1. 6.1.1.3.1 IEEE 1588 Event Triggering
          2. 6.1.1.3.2 IEEE 1588 Event Timestamping
        4. 6.1.1.4 PTP Interrupts
        5. 6.1.1.5 GPIO
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 TPI Network Circuit
        2. 6.2.1.2 Fiber Network Circuit
        3. 6.2.1.3 ESD Protection
        4. 6.2.1.4 Clock In (X1) Recommendations
          1. 6.2.1.4.1 Oscillator
          2. 6.2.1.4.2 Crystal
        5. 6.2.1.5 Magnetics
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 MAC Interface (MII/RMII)
          1. 6.2.2.1.1 Termination Requirement
          2. 6.2.2.1.2 Recommended Maximum Trace Length
        2. 6.2.2.2 Calculating Impedance
          1. 6.2.2.2.1 Microstrip Impedance - Single-Ended
          2. 6.2.2.2.2 Stripline Impedance - Single-Ended
          3. 6.2.2.2.3 Microstrip Impedance - Differential
          4. 6.2.2.2.4 Stripline Impedance - Differential
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 PCB Layout Considerations
        2. 6.3.1.2 PCB Layer Stacking
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Pin Configuration and Functions

The DP83640 pins are classified into the following interface categories (each interface is described in the sections that follow):

  • Serial Management Interface
  • MAC Data Interface
  • Clock Interface
  • LED Interface
  • IEEE 1588 Event/Trigger/Clock Interface
  • JTAG Interface
  • Reset and Power Down
  • Strap Options
  • 10/100 Mb/s PMD Interface
  • Power Supply Pins

NOTE

Strapping pin option. See Section 3.10 for strap definitions.

All DP83640 signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin.

    Type: IInput
    Type: OOutput
    Type: I/OInput/Output
    Type: ODOpen Drain
    Type: PD,PU Internal Pulldown/Pullup
    Type: SStrapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap value is to be changed then an external 2.2-kΩ resistor should be used. See Section 3.10 for details.)

3.1 Pin Layout

PT048 Package
48-Pin LQFP
Top View

DP83640 30011219.gif

3.2 Package Pin Assignments

PIN PIN
NAME NO. NAME NO.
ANA33VDD 19 RESET_N 29
ANAVSS 18 RX_CLK 38
CD_VSS 15 RX_DV 39
CLK_OUT 24 RX_ER 41
COL 42 RXD_0 46
CRS/CRS_DV 40 RXD_1 45
GPIO1 21 RXD_2 44
GPIO2 22 RXD_3 43
GPIO3 23 TCK 8
GPIO4 25 TD- 16
GPIO8 36 TD+ 17
GPIO9 37 TDI 12
IO_CORE_VSS 35 TDO 9
IO_VDD 32 TRST# 11
IO_VDD 48 TX_CLK 1
IO_VSS 47 TX_EN 2
LED_ACT 26 TXD_0 3
LED_LINK 28 TXD_1 4
LED_SPEED/FX_SD 27 TXD_2 5
MDC 31 TXD_3 6
MDIO 30 TMS 10
PWRDOWN/INTN 7 VREF 20
RD- 13 X1 34
RD+ 14 X2 33

3.3 Serial Management Interface (SMI)

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
MDC MDC I 31 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.
MDIO MDIO I/O 30 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5-kΩ pullup resistor. Alternately, an internal pullup may be enabled by setting bit 3 in the CDCTRL1 register.

3.4 MAC Data Interface

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
TX_CLK TX_CLK O 1 MII TRANSMIT CLOCK: 25-MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25-MHz reference clock. The MAC should source TX_EN and TXD[3:0] using this clock.
RMII MODE: Unused in RMII Slave mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. For RMII Master mode, the device outputs the internally generated 50-MHz reference clock on this pin.
This pin provides an integrated 50-Ω signal termination, making external termination resistors unnecessary.
TX_EN TX_EN I, PD 2 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
TXD_0
TXD_1
TXD_2
TXD_3		 TXD_0
TXD_1
TXD_2
TXD_3		 I
I
I
I, PD		 3
4
5
6		 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50-MHz reference clock.
RX_CLK RX_CLK O 38 MII RECEIVE CLOCK: Provides the 25-MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
RMII MODE: Unused in RMII Slave mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive. For RMII Master mode, the device outputs the internally generated 50-MHz reference clock on this pin.
This pin provides an integrated 50-Ω signal termination, making external termination resistors unnecessary.
RX_DV RX_DV O, PD 39 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0].
RMII RECEIVE DATA VALID: This signal provides the RMII Receive Data Valid indication independent of Carrier Sense.
This pin provides an integrated 50-Ω signal termination, making external termination resistors unnecessary.
RX_ER RX_ER S, O, PU 41 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever a media error is detected, and RX_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in RMII mode because the PHY is required to corrupt data on a receive error.
This pin provides an integrated 50-Ω signal termination, making external termination resistors unnecessary.
RXD_0
RXD_1
RXD_2
RXD_3		 RXD_0
RXD_1
RXD_2
RXD_3		 S, O, PD 46
45
44
43		 MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK (25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the 50-MHz reference clock.
These pins provide integrated 50-Ω signal terminations, making external termination resistors unnecessary.
CRS/CRS_DV CRS/CRS_DV S, O, PU 40 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
This pin provides an integrated 50-Ω signal termination, making external termination resistors unnecessary.
COL COL S, O, PU 42 MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half-Duplex Modes.
While in 10BASE-T Half-Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1 µs at the end of transmission to indicate heartbeat (SQE test).
In Full-Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full-duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision.
This pin provides an integrated 50-Ω signal termination, making external termination resistors unnecessary.

3.5 Clock Interface

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
X1 X1 I 34 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83640 and must be connected to a 25-MHz 0.005% (±50 ppm) clock source. The DP83640 supports either an external crystal resonator connected across pins X1 and X2 or an external CMOS-level oscillator source connected to pin X1 only.
RMII REFERENCE CLOCK: For RMII Slave Mode, this pin must be connected to a 50-MHz 0.005% (±50 ppm) CMOS-level oscillator source. In RMII Master Mode, a 25-MHz reference is required, either from an external crystal resonator connected across pins X1 and X2 or from an external CMOS-level oscillator source connected to pin X1 only.
X2 X2 O 33 CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25-MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used.
CLK_OUT CLK_OUT I/O, PD 24 CLOCK OUTPUT: This pin provides a highly configurable system clock, which may have one of four sources:
  1. Relative to the internal PTP clock, with a default frequency of 25 MHz (default)
  2. 50-MHz RMII reference clock in RMII Master Mode
  3. 25-MHz Receive Clock (same as RX_CLK) in 100-Mb mode
  4. 25-MHz or 50-MHz pass-through of X1 reference clock

CLOCK INPUT: This pin is used to input an external IEEE 1588 reference clock for use by the IEEE 1588 logic. The CLK_OUT_EN strap should be disabled in the system to prevent possible contention. The PTP_CLKSRC register must be configured prior to enabling the IEEE 1588 function in order to allow correct operation.

3.6 LED Interface

The DP83640 supports three configurable LED pins. The LEDs support two operational modes which are selected by the LED mode strap and a third operational mode which is register configurable. The definitions for the LEDs for each mode are detailed below.

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
LED_LINK LED_LINK S, O, PU 28 LINK LED: In Mode 1, this pin indicates the status of the LINK.
The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.
LED_SPEED LED_SPEED/FX_SD S, O, PU 27 SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in 10 Mb/s. Functionality of this LED is independent of mode selected.
LED_ACT LED_ACT S, O, PU 26 ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when
activity is present on either Transmit or Receive.
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. In Mode 3, this LED output indicates Full-Duplex status.

3.7 IEEE 1588 Event/Trigger/Clock Interface

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
GPIO1
GPIO2
GPIO3
GPIO4		 GPIO1
GPIO2
GPIO3
GPIO4		 I/O, PD 21
22
23
25		 General Purpose I/O: These pins may be used to signal or detect events.
GPIO5
GPIO6
 
GPIO7		 LED_ACT
LED_SPEED/FX_SD
LED_LINK		 I/O, PU 26
27
 
28		 General Purpose I/O: These pins may be used to signal or detect events. Care should be taken when designing systems that use LEDs but use these pins as GPIOs. To disable the LED functions, refer to Section 5.6.1.2.5.
GPIO8
GPIO9		 GPIO8
GPIO9		 I/O, PD 36
37		 General Purpose I/O: These pins may be used to signal or detect events.
GPIO10
GPIO11		 TDO
TDI		 I/O, PU 9
12		 General Purpose I/O: These pins may be used to signal or detect events. Care should be taken when designing systems that use the JTAG interface but use these pins as GPIOs.
GPIO12 CLK_OUT I/O, PD 24 General Purpose I/O: This pin may be used to signal or detect events or may output a programmable clock signal synchronized to the internal IEEE 1588 clock or may be used as an input for an externally generated IEEE 1588 reference clock. If the system does not require the CLK_OUT signal, the CLK_OUT output should be disabled through the CLK_OUT_EN strap.

3.8 JTAG Interface

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
TCK TCK I, PU 8 TEST CLOCK
This pin has a weak internal pullup.
TDO TDO O 9 TEST OUTPUT
TMS TMS I, PU 10 TEST MODE SELECT
This pin has a weak internal pullup.
TRST# TRST# I, PU 11 TEST RESET: Active low test reset.
This pin has a weak internal pullup.
TDI TDI I, PU 12 TEST DATA INPUT
This pin has a weak internal pullup.

3.9 Reset and Power Down

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
RESET_N RESET_N I, PU 29 RESET: Active Low input that initializes or re-initializes the DP83640. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Register Block section. All strap options are re-initialized as well.
PWRDOWN/INTN PWRDOWN/INTN I, PU 7 The default function of this pin is POWER DOWN.
POWER DOWN: Asserting this signal low enables the DP83640 Power Down mode of operation. In this mode, the DP83640 will power down and consume minimum power. Register access will be available through the Management Interface to configure and power up the device.
INTERRUPT: This pin may be programmed as an interrupt output instead of a Powerdown input. In this mode, Interrupts will be asserted low using this pin. Register access is required for the pin to be used as an interrupt mechanism. See Section 5.3.6.2 for more details on the interrupt mechanisms.

3.10 Strap Options

The DP83640 uses many of the functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap options are internally reloaded from the values sampled at power up or hard reset. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

A 2.2-kΩ resistor should be used for pulldown or pullup to change the default strap option. If the default option is required, then there is no need for external pullup or pulldown resistors. Because these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4		 COL
RXD_3
RXD_2
RXD_1
RXD_0		 S, O, PU
S, O, PD
S, O, PD
S, O, PD
S, O, PD		 42
43
44
45
46		 PHY ADDRESS [4:0]: The DP83640 provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset.
The DP83640 supports PHY Address strapping values 0 (<00000>) through 31 (<11111>).A PHY Address of 0 puts the part into the MII Isolate Mode. The MII isolate mode must be selected by strapping PHY Address 0; changing to Address 0 by register write will not put the PHY in the MII isolate mode.
PHYAD[0] pin has weak internal pullup resistor.
PHYAD[4:1] pins have weak internal pulldown resistors.
AN_EN
AN1
 
AN0		 LED_LINK
LED_SPEED/FX_SD
LED_ACT		 S, O, PU
S, O, PU
 
S, O, PU		 28
27
 
26		 AUTO-NEGOTIATION ENABLE: When high, this enables Auto-Negotiation with the capability set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins.
AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83640 according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2-kΩ resistors. These pins should NEVER be connected directly to GND or VCC.
The value set at this input is latched into the DP83640 at Hardware-Reset.
The float/pulldown status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 111 because these pins have internal pullups.
FIBER MODE DUPLEX SELECTION: If Fiber mode is strapped using the FX_EN_Z pin (FX_EN_Z = 0), the AN0 strap value is used to select half or full duplex. AN_EN and AN1 are ignored in Fiber mode because it is 100 Mb only and does not support Auto-Negotiation. In Fiber mode, AN1 should not be connected to any system components except the fiber transceiver.
FX_EN_Z AN_EN AN1 AN0 Forced Mode
1 0 0 0 10BASE-T, Half-Duplex
1 0 0 1 10BASE-T, Full-Duplex
1 0 1 0 100BASE-TX, Half-Duplex
1 0 1 1 100BASE-TX, Full-Duplex
0 X X 0 100BASE-FX, Half-Duplex
0 X X 1 100BASE-FX, Full-Duplex
FX_EN_Z AN_EN AN1 AN0 Advertised Mode
1 1 0 0 10BASE-T, Half/Full-Duplex
1 1 0 1 100BASE-TX, Half/Full-Duplex
1 1 1 0 100BASE-TX, Full-Duplex
1 1 1 1 10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
CLK_OUT_EN GPIO1 S, I, PD 21 CLK_OUT OUTPUT ENABLE: When high, enables clock output on the CLK_OUT pin at power-up.
FX_EN_Z RX_ER S, O, PU 41 FX ENABLE: This strapping option enables 100Base-FX (Fiber) mode. This mode is disabled by default. An external pulldown will enable 100Base-FX mode.
LED_CFG CRS/CRS_DV S, O, PU 40 LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled through the strap option. All modes are configurable through register access.
See Table 5-2 for LED Mode Selection.
MII_MODE RX_DV S, O, PD 39 MII MODE SELECT: This strapping option determines the operating mode of the MAC Data Interface. Default operation is MII Mode with a value of 0 due to the internal pulldown. Strapping MII_MODE high will cause the device to be in RMII mode of operation.
 
MII_MODE MAC Interface Mode
0 MII Mode
1 RMII Mode
PCF_EN GPIO2 S, I, PD 22 PHY CONTROL FRAME ENABLE: When high, allows the DP83640 to respond to PHY Control Frames.
RMII_MAS TXD_3 S, I, PD 6 RMII MASTER ENABLE: When MII_MODE is strapped high, this strapping option enables RMII Master mode, in which the DP83640 uses a 25-MHz crystal connection on X1/X2 and generates the 50-MHz RMII reference clock. If strapped low when MII_MODE is strapped high, default RMII operation (RMII Slave) is enabled, in which the DP83640 uses a 50 MHz oscillator input on X1 as the RMII reference clock. This strap option is ignored if the MII_MODE strap is low.

3.11 10 Mb/s and 100 Mb/s PMD Interface

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
TD-
TD+		 TD-
TD+		 I/O 16
17		 Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling.
In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Transmit pair.
These pins require 3.3-V bias for operation.
RD-
RD+		 RD-
RD+		 I/O 13
14		 Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Receive pair.
These pins require 3.3-V bias for operation.
FX_SD LED_SPEED/FX_SD S, I/O, PU 27 FIBER MODE SIGNAL DETECT: This pin provides the Signal Detect input for 100BASE-FX mode.

3.12 Power Supply Pins

SIGNAL NAME PIN NAME TYPE PIN # DESCRIPTION
ANAVSS ANAVSS Ground 18 Analog Ground
ANA33VDD ANA33VDD Supply 19 Analog VDD Supply
CD_VSS CD_VSS Ground 15 Analog Ground
IO_CORE_VSS IO_CORE_VSS Ground 35 Digital Ground
IO_VDD IO_VDD Supply 32
48		 I/O VDD Supply
IO_VSS IO_VSS Ground 47 Digital Ground
VREF VREF 20 Bias Resistor Connection. A 4.87-kΩ 1% resistor should be connected from VREF to GND.