JAJSC32E September   2012  – June 2019 DP83848-EP

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
      1.      代表的なシステム図
  2. 2 改訂履歴
  3. 3 Pin Configuration and Functions
    1. 3.1 Package Pin Assignments
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Specifications
      1. 4.5.1 Electrical Characteristics
    6. 4.6 AC Specifications
      1. 4.6.1  Power Up Timing
      2. 4.6.2  Reset Timing
      3. 4.6.3  MII Serial Management Timing
      4. 4.6.4  100-Mbps MII Transmit Timing
      5. 4.6.5  100-Mbps MII Receive Timing
      6. 4.6.6  100BASE-TX Transmit Packet Latency Timing
      7. 4.6.7  100BASE-TX Transmit Packet Deassertion Timing
      8. 4.6.8  100BASE-TX Transmit Timing (tR/F and Jitter)
      9. 4.6.9  100BASE-TX Receive Packet Latency Timing
      10. 4.6.10 100BASE-TX Receive Packet Deassertion Timing
      11. 4.6.11 10-Mbps MII Transmit Timing
      12. 4.6.12 10-Mbps MII Receive Timing
      13. 4.6.13 10-Mbps Serial Mode Transmit Timing
      14. 4.6.14 10-Mbps Serial Mode Receive Timing
      15. 4.6.15 10BASE-T Transmit Timing (Start of Packet)
      16. 4.6.16 10BASE-T Transmit Timing (End of Packet)
      17. 4.6.17 10BASE-T Receive Timing (Start of Packet)
      18. 4.6.18 10BASE-T Receive Timing (End of Packet)
      19. 4.6.19 10-Mbps Heartbeat Timing
      20. 4.6.20 10-Mbps Jabber Timing
      21. 4.6.21 10BASE-T Normal Link Pulse Timing
      22. 4.6.22 Auto-Negotiation Fast Link Pulse (FLP) Timing
      23. 4.6.23 100BASE-TX Signal Detect Timing
      24. 4.6.24 100-Mbps Internal Loopback Timing
      25. 4.6.25 10-Mbps Internal Loopback Timing
      26. 4.6.26 RMII Transmit Timing
      27. 4.6.27 RMII Receive Timing
      28. 4.6.28 Isolation Timing
      29. 4.6.29 25MHz_OUT Timing
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Auto-Negotiation
        1. 5.3.1.1 Auto-Negotiation Pin Control
        2. 5.3.1.2 Auto-Negotiation Register Control
        3. 5.3.1.3 Auto-Negotiation Parallel Detection
        4. 5.3.1.4 Auto-Negotiation Restart
        5. 5.3.1.5 Enabling Auto-Negotiation via Software
        6. 5.3.1.6 Auto-Negotiation Complete Time
      2. 5.3.2 Auto-MDIX
      3. 5.3.3 LED Interface
        1. 5.3.3.1 LEDs
        2. 5.3.3.2 LED Direct Control
      4. 5.3.4 Internal Loopback
      5. 5.3.5 BIST
      6. 5.3.6 Energy Detect Mode
    4. 5.4 Device Functional Modes
      1. 5.4.1 MII Interface
        1. 5.4.1.1 Nibble-wide MII Data Interface
        2. 5.4.1.2 Collision Detect
        3. 5.4.1.3 Carrier Sense
      2. 5.4.2 Reduced MII Interface
        1. 5.4.2.1 10 Mb Serial Network Interface (SNI)
      3. 5.4.3 802.3u MII Serial Management Interface
        1. 5.4.3.1 Serial Management Register Access
        2. 5.4.3.2 Serial Management Access Protocol
        3. 5.4.3.3 Serial Management Preamble Suppression
      4. 5.4.4 PHY Address
        1. 5.4.4.1 MII Isolate Mode
      5. 5.4.5 Half Duplex vs Full Duplex
      6. 5.4.6 Reset Operation
        1. 5.4.6.1 Hardware Reset
        2. 5.4.6.2 Software Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-Group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
        2. 5.5.1.2 100BASE-TX Receiver
          1. 5.5.1.2.1  Analog Front End
          2. 5.5.1.2.2  Digital Signal Processor
            1. 5.5.1.2.2.1 Digital Adaptive Equalization and Gain Control
            2. 5.5.1.2.2.2 Base Line Wander Compensation
          3. 5.5.1.2.3  Signal Detect
          4. 5.5.1.2.4  MLT-3 to NRZI Decoder
          5. 5.5.1.2.5  NRZI to NRZ
          6. 5.5.1.2.6  Serial to Parallel
          7. 5.5.1.2.7  Descrambler
          8. 5.5.1.2.8  Code-group Alignment
          9. 5.5.1.2.9  4B/5B Decoder
          10. 5.5.1.2.10 100BASE-TX Link Integrity Monitor
          11. 5.5.1.2.11 Bad SSD Detection
        3. 5.5.1.3 10BASE-T Transceiver Module
          1. 5.5.1.3.1  Operational Modes
            1. 5.5.1.3.1.1 Half Duplex Mode
            2. 5.5.1.3.1.2 Full Duplex Mode
          2. 5.5.1.3.2  Smart Squelch
          3. 5.5.1.3.3  Collision Detection and SQE
          4. 5.5.1.3.4  Carrier Sense
          5. 5.5.1.3.5  Normal Link Pulse Detection and Generation
          6. 5.5.1.3.6  Jabber Function
          7. 5.5.1.3.7  Automatic Link Polarity Detection and Correction
          8. 5.5.1.3.8  Transmit and Receive Filtering
          9. 5.5.1.3.9  Transmitter
          10. 5.5.1.3.10 Receiver
    6. 5.6 Memory
      1. 5.6.1 Register Definition
        1. 5.6.1.1 Basic Mode Control Register (BMCR)
        2. 5.6.1.2 Basic Mode Status Register (BMSR)
        3. 5.6.1.3 PHY Identifier Register #1 (PHYIDR1)
        4. 5.6.1.4 PHY Identifier Register #2 (PHYIDR2)
        5. 5.6.1.5 Auto-Negotiation Advertisement Register (ANAR)
        6. 5.6.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.6.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 5.6.1.8 Auto-Negotiate Expansion Register (ANER)
        9. 5.6.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
      2. 5.6.2 Extended Registers
        1. 5.6.2.1  PHY Status Register (PHYSTS)
        2. 5.6.2.2  MII Interrupt Control Register (MICR)
        3. 5.6.2.3  MII Interrupt Status and Miscellaneous Control Register (MISR)
        4. 5.6.2.4  False Carrier Sense Counter Register (FCSCR)
        5. 5.6.2.5  Receiver Error Counter Register (RECR)
        6. 5.6.2.6  100 Mbps PCS Configuration and Status Register (PCSR)
        7. 5.6.2.7  RMII and Bypass Register (RBR)
        8. 5.6.2.8  LED Direct Control Register (LEDCR)
        9. 5.6.2.9  PHY Control Register (PHYCR)
        10. 5.6.2.10 10Base-T Status/Control Register (10BTSCR)
        11. 5.6.2.11 CD Test and BIST Extensions Register (CDCTRL1)
        12. 5.6.2.12 Energy Detect Control (EDCR)
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 TPI Network Circuit
        2. 6.2.1.2 Clock IN (X1) Requirements
        3. 6.2.1.3 Power Feedback Circuit
        4. 6.2.1.4 Power Down and Interrupt
          1. 6.2.1.4.1 Power Down Control Mode
          2. 6.2.1.4.2 Interrupt Mechanisms
        5. 6.2.1.5 Magnetics
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 MAC Interface (MII/RMII)
        2. 6.2.2.2 Termination Requirement
        3. 6.2.2.3 Recommended Maximum Trace Length
        4. 6.2.2.4 Calculating Impedance
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 PCB Layout Considerations
      2. 8.1.2 PCB Layer Stacking
    2. 8.2 Layout Example
    3. 8.3 Thermal Vias Recommendation
  9. 9 デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 関連資料
    2. 9.2 Community Resources
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 Export Control Notice
    6. 9.6 Glossary
  10. 10メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3.1 Package Pin Assignments

Table 3-1 Package Pin Assignments

PIN NUMBER PIN NAME
1 TX_CLK
2 TX_EN
3 TXD_0
4 TXD_1
5 TXD_2
6 SNI_MODE(TXD_3)
7 PWR_DOWN(INT)
8 TCK
9 TDO
10 TMS
11 TRST
12 TDI
13 RD–
14 RD+
15 AGND
16 TD–
17 TD+
18 PFBIN1
19 AGND
20 RESERVED
21 RESERVED
22 AVDD33
23 PFBOUT
24 RBIAS
25 25MHz_OUT
26 AN_EN(LED_ACT/COL)
27 AN_1(LED_SPEED)
28 AN_0(LED_LINK)
29 RESET_N
30 MDIO
31 MDC
32 IOVDD33
33 X2
34 X1
35 IOGND
36 DGND
37 PFBIN2
38 RX_CLK
39 RX_DV(MII_MODE)
40 CRS/CRS_DV(LED_CFG)
41 MDIX_EN(RX_ER)
42 PHYAD0(COL)
43 PHYAD1(RXD_0)
44 PHYAD2(RXD_1)
45 PHYAD3(RXD_2)
46 PHYAD4(RXD_3)
47 IOGND
48 IOVDD33
49 DAP (Die Attach Pad/Thermal Pad)

Table 3-2 Serial Management Interface

TERMINAL I/O DESCRIPTION
NAME NO.
MDC 31 I MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.
MDIO 30 I/O MANAGEMENT DATA I/O: Bi-directional management instruction/ data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5-kΩ pullup resistor.

Table 3-3 MAC Data Interface

TERMINAL I/O DESCRIPTION
NAME NO.
TX_CLK 1 O MII TRANSMIT CLOCK: 25-MHz transmit clock output in 100-Mbps mode or 2.5 MHz in 10-Mbps mode derived from the 25-MHz reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive.
SNI TRANSMIT CLOCK: 10-MHz transmit clock output in 10-Mb SNI mode. The MAC should source TX_EN and TXD_0 using this clock.
TX_EN 2 I, PD MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0.
TXD_0 3 I MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10-Mbps mode or 25 MHz in 100-Mbps mode).
TXD_1 4 RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50-MHz reference clock.
TXD_2 5 SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK (10 MHz in 10-Mbps SNI mode).
TXD_3 6 S, I, PD
RX_CLK 38 O MII RECEIVE CLOCK: Provides the 25-MHz recovered receive clocks for 100-Mbps mode and 2.5 MHz for 10-Mbps mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10-MHz recovered receive clocks for 10-Mbps SNI mode.
RX_DV 39 S, O, PD MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0]. MII mode by default with internal pulldown.
RMII Synchronous Receive Data Valid: This signal provides the RMII Receive Data Valid indication independent of Carrier Sense.
This pin is not used in SNI mode.
RX_ER 41 S, O, PU MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100-Mbps mode.
RMII RECEIVE ERROR: Assert high synchronously to X1 whenever it detects a media error and RXDV is asserted in 100-Mbps mode.
This pin is not required to be used by a MAC, in either MII or RMII mode, since the Phy is required to corrupt data on a receive error.
This pin is not used in SNI mode.
RXD_0 43 S, O, PD MII RECEIVE DATA: Nibble-wide receive data signals driven synchronously to the RX_CLK (25 MHz for 100-Mbps mode, 2.5 MHz for 10-Mbps mode). RXD[3:0] signals contain valid data when RX_DV is asserted.
RXD_1 44 RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz.
RXD_2 45 SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode.
RXD_3 46
CRS/CRS_DV 40 S, O, PU MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to frame valid receive data on the RXD_0 signal.
COL 42 S, O, PU MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10-Mbps and 100-Mbps Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1 µs at the end of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10-Mbps or 100-Mbps operation, this signal is always logic 0. There is no heartbeat function during 10-Mbps full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision.
SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10-Mbps SNI mode.

Table 3-4 Clock Interface

TERMINAL I/O DESCRIPTION
NAME NO.
X1 34 I CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848-EP and must be connected to a 25-MHz 0.005% (±50 ppm) clock source. The DP83848-EP supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50-MHz 0.005% (±50 ppm) CMOS-level oscillator source.
X2 33 O CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25-MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used.
25MHz_OUT 25 O 25-MHz CLOCK OUTPUT:
In MII mode, this pin provides a 25-MHz clock output to the system.
In RMII mode, this pin provides a 50-MHz clock output to the system.
This allows other devices to use the reference clock from the DP83848-EP without requiring additional clock sources.

Table 3-5 LED Interface

TERMINAL I/O DESCRIPTION
NAME NO.
LED_LINK 28 S, O, PU LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.
LED_SPEED 27 S, O, PU SPEED LED: The LED is ON when device is in 100 Mbps and OFF when in 10 Mbps. Functionality of this LED is independent of mode selected.
LED_ACT/COL 26 S, O, PU ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or Receive.
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be programmed to indicate Full-duplex status instead of Collision.

Table 3-6 JTAG Interface

TERMINAL I/O DESCRIPTION
NAME NO.
TCK 8 I, PU TEST CLOCK: This pin has a weak internal pullup.
TDI 12 I, PU TEST DATA INPUT: This pin has a weak internal pullup.
TDO 9 O TEST OUTPUT
TMS 10 I, PU TEST MODE SELECT: This pin has a weak internal pullup.
TRST 11 I, PU TEST RESET: Active low asynchronous test reset. This pin has a weak internal pullup.

Table 3-7 Reset and Power Down

TERMINAL I/O DESCRIPTION
NAME NO.
RESET_N 29 I, PU RESET: Active Low input that initializes or re-initializes the DP83848-EP. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in Section 5.6. All strap options are re-initialized as well.
PWR_DOWN/INT 7 I, OD, PU The default function of this pin is POWER DOWN.
POWER DOWN: The pin is an active low input in this mode and should be asserted low to put the device in a Power Down mode.
INTERRUPT: The pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs. Although the pin has a weak internal pullup, some applications may require an external pullup resister. Register access is required for the pin to be used as an interrupt mechanism. See Section 6.2.1.4.2 for more details on the interrupt mechanisms.

Table 3-8 Strap Options(1)(2)

TERMINAL I/O DESCRIPTION
NAME NO.
PHYAD0 (COL) 42 S, O, PU PHY ADDRESS [4:0]: The DP83848-EP provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset.
PHYAD1 (RXD_0) 43 S, O, PD The DP83848-EP supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). A PHY Address of 0 puts the part into the MII Isolate Mode. The MII isolate mode must be selected by strapping Phy Address 0; changing to Address 0 by register write will not put the Phy in the MII isolate mode. Please refer to Section 5.4.4.1 for additional information.
PHYAD2 (RXD_1) 44 PHYAD0: This pin has weak internal pullup resistor.
PHYAD3 (RXD_2) 45 PHYAD[4:1]: These pins have weak internal pulldown resistors.
PHYAD4 (RXD_3) 46
AN_EN (LED_ACT/COL) 26 S, O, PU Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by ANO and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins.
AN_1 (LED_SPEED) 27 AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83848-EP according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2-kΩ resistors. These pins should NEVER be connected directly to GND or VCC.
AN_0 (LED_LINK) 28 The value set at this input is latched into the DP83848-EP at Hardware-Reset.
The float/pulldown status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 111 since these pins have internal pullups.
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
1 1 0 10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
MII_MODE (RX_DV) 39 S, O, PD MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default operation (No pullups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII or SNI mode of operation, determined by the status of the SNI_MODE strap. Since the pins include internal pulldowns, the default values are 0.
SNI_MODE (TXD_3) 6 The following table details the configurations:
MII_MODE SNI_MODE MAC Interface Mode
0 X MII Mode
1 0 RMII Mode
1 1 10-Mb SNI Mode
LED_CFG (CRS) 40 S, O, PU LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option. All modes are configurable via register access.
See Table 5-2 for LED Mode Selection.
MDIX_EN (RX_ER) 41 S, O, PU MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pulldown will disable Auto- MDIX mode.
(1) The DP83848-EP uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The functional pin name is indicated in parentheses.
(2) A 2.2-kΩ resistor should be used for pulldown or pullup to change the default strap option. If the default option is required, then there is no need for external pullup or pulldown resistors. Since these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.

Table 3-9 10-Mbps and 100-Mbps PMD Interface

TERMINAL I/O DESCRIPTION
NAME NO.
TD–, TD+ 16, 17 I/O Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling.
In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.
These pins require 3.3-V bias for operation.
RD–, RD+ 13, 14 I/O Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.
These pins require 3.3-V bias for operation.

Table 3-10 Special Connections

TERMINAL I/O DESCRIPTION
NAME NO.
RBIAS 24 I Bias Resistor Connection. A 4.87-kΩ 1% resistor should be connected from RBIAS to GND.
PFBOUT 23 O Power Feedback Output. Parallel caps, 10 µF (Tantalum preferred) and 0.1 µF, should be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See Section 6.2.1.3 for proper placement pin.
PFBIN1 18 I Power Feedback Input. These pins are fed with power from PFBOUT pin. A small capacitor of 0.1 µF should be connected close to each pin.
PFBIN2 37 Note: Do not supply power to these pins other than from PFBOUT.
RESERVED 20, 21 I/O RESERVED: These pins must be pulled-up through 2.2-kΩ resistors to AVDD33 supply.

Table 3-11 Power Supply Pins

TERMINAL DESCRIPTION
NAME NO.
IOVDD33 32, 48 I/O 3.3-V supply
IOGND 35, 47 I/O ground
DGND 36 Digital ground
AVDD33 22 Analog 3.3-V supply
AGND 15, 19 Analog ground
GNDPAD DAP Thermal pad