JAJSC32E September   2012  – June 2019 DP83848-EP

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
      1.      代表的なシステム図
  2. 2 改訂履歴
  3. 3 Pin Configuration and Functions
    1. 3.1 Package Pin Assignments
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Specifications
      1. 4.5.1 Electrical Characteristics
    6. 4.6 AC Specifications
      1. 4.6.1  Power Up Timing
      2. 4.6.2  Reset Timing
      3. 4.6.3  MII Serial Management Timing
      4. 4.6.4  100-Mbps MII Transmit Timing
      5. 4.6.5  100-Mbps MII Receive Timing
      6. 4.6.6  100BASE-TX Transmit Packet Latency Timing
      7. 4.6.7  100BASE-TX Transmit Packet Deassertion Timing
      8. 4.6.8  100BASE-TX Transmit Timing (tR/F and Jitter)
      9. 4.6.9  100BASE-TX Receive Packet Latency Timing
      10. 4.6.10 100BASE-TX Receive Packet Deassertion Timing
      11. 4.6.11 10-Mbps MII Transmit Timing
      12. 4.6.12 10-Mbps MII Receive Timing
      13. 4.6.13 10-Mbps Serial Mode Transmit Timing
      14. 4.6.14 10-Mbps Serial Mode Receive Timing
      15. 4.6.15 10BASE-T Transmit Timing (Start of Packet)
      16. 4.6.16 10BASE-T Transmit Timing (End of Packet)
      17. 4.6.17 10BASE-T Receive Timing (Start of Packet)
      18. 4.6.18 10BASE-T Receive Timing (End of Packet)
      19. 4.6.19 10-Mbps Heartbeat Timing
      20. 4.6.20 10-Mbps Jabber Timing
      21. 4.6.21 10BASE-T Normal Link Pulse Timing
      22. 4.6.22 Auto-Negotiation Fast Link Pulse (FLP) Timing
      23. 4.6.23 100BASE-TX Signal Detect Timing
      24. 4.6.24 100-Mbps Internal Loopback Timing
      25. 4.6.25 10-Mbps Internal Loopback Timing
      26. 4.6.26 RMII Transmit Timing
      27. 4.6.27 RMII Receive Timing
      28. 4.6.28 Isolation Timing
      29. 4.6.29 25MHz_OUT Timing
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Auto-Negotiation
        1. 5.3.1.1 Auto-Negotiation Pin Control
        2. 5.3.1.2 Auto-Negotiation Register Control
        3. 5.3.1.3 Auto-Negotiation Parallel Detection
        4. 5.3.1.4 Auto-Negotiation Restart
        5. 5.3.1.5 Enabling Auto-Negotiation via Software
        6. 5.3.1.6 Auto-Negotiation Complete Time
      2. 5.3.2 Auto-MDIX
      3. 5.3.3 LED Interface
        1. 5.3.3.1 LEDs
        2. 5.3.3.2 LED Direct Control
      4. 5.3.4 Internal Loopback
      5. 5.3.5 BIST
      6. 5.3.6 Energy Detect Mode
    4. 5.4 Device Functional Modes
      1. 5.4.1 MII Interface
        1. 5.4.1.1 Nibble-wide MII Data Interface
        2. 5.4.1.2 Collision Detect
        3. 5.4.1.3 Carrier Sense
      2. 5.4.2 Reduced MII Interface
        1. 5.4.2.1 10 Mb Serial Network Interface (SNI)
      3. 5.4.3 802.3u MII Serial Management Interface
        1. 5.4.3.1 Serial Management Register Access
        2. 5.4.3.2 Serial Management Access Protocol
        3. 5.4.3.3 Serial Management Preamble Suppression
      4. 5.4.4 PHY Address
        1. 5.4.4.1 MII Isolate Mode
      5. 5.4.5 Half Duplex vs Full Duplex
      6. 5.4.6 Reset Operation
        1. 5.4.6.1 Hardware Reset
        2. 5.4.6.2 Software Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-Group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
        2. 5.5.1.2 100BASE-TX Receiver
          1. 5.5.1.2.1  Analog Front End
          2. 5.5.1.2.2  Digital Signal Processor
            1. 5.5.1.2.2.1 Digital Adaptive Equalization and Gain Control
            2. 5.5.1.2.2.2 Base Line Wander Compensation
          3. 5.5.1.2.3  Signal Detect
          4. 5.5.1.2.4  MLT-3 to NRZI Decoder
          5. 5.5.1.2.5  NRZI to NRZ
          6. 5.5.1.2.6  Serial to Parallel
          7. 5.5.1.2.7  Descrambler
          8. 5.5.1.2.8  Code-group Alignment
          9. 5.5.1.2.9  4B/5B Decoder
          10. 5.5.1.2.10 100BASE-TX Link Integrity Monitor
          11. 5.5.1.2.11 Bad SSD Detection
        3. 5.5.1.3 10BASE-T Transceiver Module
          1. 5.5.1.3.1  Operational Modes
            1. 5.5.1.3.1.1 Half Duplex Mode
            2. 5.5.1.3.1.2 Full Duplex Mode
          2. 5.5.1.3.2  Smart Squelch
          3. 5.5.1.3.3  Collision Detection and SQE
          4. 5.5.1.3.4  Carrier Sense
          5. 5.5.1.3.5  Normal Link Pulse Detection and Generation
          6. 5.5.1.3.6  Jabber Function
          7. 5.5.1.3.7  Automatic Link Polarity Detection and Correction
          8. 5.5.1.3.8  Transmit and Receive Filtering
          9. 5.5.1.3.9  Transmitter
          10. 5.5.1.3.10 Receiver
    6. 5.6 Memory
      1. 5.6.1 Register Definition
        1. 5.6.1.1 Basic Mode Control Register (BMCR)
        2. 5.6.1.2 Basic Mode Status Register (BMSR)
        3. 5.6.1.3 PHY Identifier Register #1 (PHYIDR1)
        4. 5.6.1.4 PHY Identifier Register #2 (PHYIDR2)
        5. 5.6.1.5 Auto-Negotiation Advertisement Register (ANAR)
        6. 5.6.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.6.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 5.6.1.8 Auto-Negotiate Expansion Register (ANER)
        9. 5.6.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
      2. 5.6.2 Extended Registers
        1. 5.6.2.1  PHY Status Register (PHYSTS)
        2. 5.6.2.2  MII Interrupt Control Register (MICR)
        3. 5.6.2.3  MII Interrupt Status and Miscellaneous Control Register (MISR)
        4. 5.6.2.4  False Carrier Sense Counter Register (FCSCR)
        5. 5.6.2.5  Receiver Error Counter Register (RECR)
        6. 5.6.2.6  100 Mbps PCS Configuration and Status Register (PCSR)
        7. 5.6.2.7  RMII and Bypass Register (RBR)
        8. 5.6.2.8  LED Direct Control Register (LEDCR)
        9. 5.6.2.9  PHY Control Register (PHYCR)
        10. 5.6.2.10 10Base-T Status/Control Register (10BTSCR)
        11. 5.6.2.11 CD Test and BIST Extensions Register (CDCTRL1)
        12. 5.6.2.12 Energy Detect Control (EDCR)
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 TPI Network Circuit
        2. 6.2.1.2 Clock IN (X1) Requirements
        3. 6.2.1.3 Power Feedback Circuit
        4. 6.2.1.4 Power Down and Interrupt
          1. 6.2.1.4.1 Power Down Control Mode
          2. 6.2.1.4.2 Interrupt Mechanisms
        5. 6.2.1.5 Magnetics
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 MAC Interface (MII/RMII)
        2. 6.2.2.2 Termination Requirement
        3. 6.2.2.3 Recommended Maximum Trace Length
        4. 6.2.2.4 Calculating Impedance
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 PCB Layout Considerations
      2. 8.1.2 PCB Layer Stacking
    2. 8.2 Layout Example
    3. 8.3 Thermal Vias Recommendation
  9. 9 デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 関連資料
    2. 9.2 Community Resources
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 Export Control Notice
    6. 9.6 Glossary
  10. 10メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5.1.1.1 Code-Group Encoding and Injection

The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. See Table 5-6 for 4B to 5B code-group mapping details.

The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of Transmit Enable signal from the MAC, the code-group encoder injects the T/R code-group pair (01101 00111) indicating the end of the frame.

After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream until the next transmit packet is detected (reassertion of Transmit Enable).