JAJSC33 データシート

JAJSC33G February 2015 – October 2022 DP83867CR , DP83867IR

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

RGZ|48
PAP|64

サーマルパッド・メカニカル・データ

PAP|64
- PPTD078J
RGZ|48
- QFND014T

発注情報

Table 6-1 Pin Functions

PIN			TYPE⁽¹⁾	DESCRIPTION
NAME	HTQFP	VQFN	TYPE⁽¹⁾	DESCRIPTION
MAC INTERFACES		RGMII
TX_CLK	30		O	MII TRANSMIT CLOCK: TX_CLK is a continuous clock signal driven by the PHY during 10 Mbps or 100 Mbps MII mode. TX_CLK clocks the data or error out of the MAC layer and into the PHY.
TX_CLK	30		O	The TX_CLK clock frequency is 2.5 MHz in 10BASE-Te and 25 MHz in 100BASE-TX mode.
TX_D7	31		I, PD	GMII TRANSMIT DATA Bit 7: This signal carries data from the MAC to the PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D6	30		I, PD	GMII TRANSMIT DATA Bit 6: This signal carries data from the MAC to the PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D5	33		I, PD	GMII TRANSMIT DATA Bit 5: This signal carries data from the MAC to the PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D4	34		I, PD	GMII TRANSMIT DATA Bit 4: This signal carries data from the MAC to the PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D3	35	25	I, PD	TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit clock TX_CLK.
TX_D2	36	26	I, PD	TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit clock TX_CLK.
TX_D1	37	27	I, PD	TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit clock TX_CLK.
TX_D0	38	28	I, PD	TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit clock TX_CLK.
TX_ER	39		I, PD	GMII TRANSMIT ERROR: This signal is used in GMII mode to force the PHY to transmit invalid symbols. The TX_ER signal is synchronous to the GMII transmit clock GTX_CLK.
				In MII 4B nibble mode, assertion of Transmit Error by the controller causes the PHY to issue invalid symbols followed by Halt (H) symbols until deassertion occurs.
				In GMII mode, assertion causes the PHY to emit one or more code-groups that are invalid data or delimiter in the transmitted frame.
GTX_CLK	40	29	I, PD	GMII and RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125 MHz.
RX_CLK	43	32	O	RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation:
				2.5 MHz in 10-Mbps mode.
				25 MHz in 100-Mbps mode.
				125 MHz in 1000-Mbps GMII and RGMII mode.
RX_D0	44	33	S, O, PD	RECIEVE DATA Bit 0: This signal carries data from the PHY to the MAC in GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D1	45	34	O, PD	RECIEVE DATA Bit 1: This signal carries data from the PHY to the MAC in GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D2	46	35	S, O, PD	RECIEVE DATA Bit 2: This signal carries data from the PHY to the MAC in GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D3	47	36	O, PD	RECIEVE DATA Bit 3: This signal carries data from the PHY to the MAC in GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D4	48		S, O, PD	RECIEVE DATA Bit 4: This signal carries data from the PHY to the MAC in GMII mode. It is synchronous to the receive clock RX_CLK.
RX_D5	49		S, O, PD	RECIEVE DATA Bit 5: This signal carries data from the PHY to the MAC in GMII mode. It is synchronous to the receive clock RX_CLK.
RX_D6	50		S, O, PD	RECIEVE DATA Bit 6: This signal carries data from the PHY to the MAC in GMII mode. It is synchronous to the receive clock RX_CLK.
RX_D7	51		S, O, PD	RECIEVE DATA Bit 7: This signal carries data from the PHY to the MAC in GMII mode. It is synchronous to the receive clock RX_CLK.
TX_EN / TX_CTRL	52	37	I, PD	TRANSMIT ENABLE or TRANSMIT CONTROL: In MII or GMII mode,it is an active high input sourced from MAC layer to indicate transmission data is available on the TXD.
TX_EN / TX_CTRL	52	37	I, PD	In RGMII mode, it combines the transmit enable and the transmit error signals of GMII mode using both clock edges.
RX_DV / RX_CTRL	53	38	S, O, PD	RECEIVE DATA VALID or RECEIVE CONTROL: In MII and GMII modes, it is asserted high to indicate that valid data is present on the corresponding RXD[3:0] in MII mode and RXD[7:0] in GMII mode.
(Straps Required)	53	38	S, O, PD	In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK).
RX_ER / GPIO			O, PD	RECEIVE ERROR: In 10 Mbps, 100 Mbps and 1000 Mbps mode this active high output indicates that the PHY has detected a Receive Error. The RX_ER signal is synchronous with the receive clock (RX_CLK).
RX_ER / GPIO			O, PD	In RGMII, the RX_ER pin is not used.
COL / GPIO			O, PD	COLLISION DETECT: Asserted high to indicate detection of a collision condition (assertion of CRS due to simultaneous transmit and receive activity) in Half-Duplex modes. This signal is not synchronous to either MII clock (GTX_CLK, TX_CLK or RX_CLK).
				This signal is not defined and stays low for Full-Duplex modes.
				In RGMII mode, COL is not used.
CRS	56		S, O, PD	CARRIER SENSE: CRS is asserted high to indicate the presence of a carrier due to receive or transmit activity in Half-Duplex mode.
				For 10BASE-Te and 100BASE-TX Full-Duplex operation CRS is asserted when a received packet is detected. This signal is not defined for 1000BASE-T Full-Duplex mode.
				In RGMII mode, CRS is not used.
GENERAL PURPOSE I/O
GPIO_0		39	S, O, PD	General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
GPIO_1		40	S, O, PD	General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
MANAGEMENT INTERFACE
MDC	20	16	I, PD	MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz and no minimum.
MDIO	21	17	I/O	MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the management station or the PHY. This pin requires pullup resistor. The IEEE specified resistor value is 1.5kΩ, but a 2.2kΩ is acceptable.
INT / PWDN	60	44	I/O, PU	INTERRUPT / POWER DOWN:
				The default function of this pin is POWER DOWN.
				POWER DOWN: Asserting this signal low enables the Power Down mode of operation. In this mode, the device will power down and consume minimum power. Register access will be available through the Management Interface to configure and power up the device.
				INTERRUPT: This pin may be programmed as an interrupt output instead of a Power down input. In this mode, Interrupts will be asserted low using this pin. When operating this pin as an interrupt, it is an open-drain architecture. Register access is required for the pin to be used as an interrupt mechanism. When operating this pin as an interrupt, an external 2.2kΩ connected to the VDDIO supply is recommended.
RESET
RESET_N	59	43	I, PU	RESET: The active low RESET initializes or re-initializes the DP83867. All internal registers will re-initialize to their default state upon assertion of RESET. The RESET input must be held low for a minimum of 1µs.
CLOCK INTERFACE
XI	19	15	I	CRYSTAL/OSCILLATOR INPUT: 25 MHz oscillator or crystal input (50 ppm)
XO	18	14	O	CRYSTAL OUTPUT: Second terminal for 25 MHz crystal. Must be left floating if a clock oscillator is used.
CLK_OUT	22	18	O	CLOCK OUTPUT: Output clock
JTAG INTERFACE
JTAG_CLK	25	20	I, PU	JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity.
JTAG_TDO	26	21	O	JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device via TDO.
JTAG_TMS	27	22	I, PU	JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction.
JTAG_TDI	28	23	I, PU	JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device via TDI.
JTAG_TRSTN	24		I, PU	JTAG TEST RESET: IEEE 1149.1 Test Reset pin, active low reset provides for asynchronous reset of the Tap Controller. This reset has no effect on the device registers.
LED INTERFACE
LED_1	62	46	S, I/O, PD	LED_1: By default, this pin indicates that 1000BASE-T link is established. Additional functionality is configurable via LEDCR1[7:4] register bits.
LED_0	63	47	S, I/O, PD	LED_0: By default, this pin indicates that link is established. Additional functionality is configurable via LEDCR1[3:0] register bits.
MEDIA DEPENDENT INTERFACE
TD_P_A	2	1	A	Differential Transmit and Receive Signals
TD_M_A	3	2	A	Differential Transmit and Receive Signals
TD_P_B	5	4	A	Differential Transmit and Receive Signals
TD_M_B	6	5	A	Differential Transmit and Receive Signals
TD_P_C	10	7	A	Differential Transmit and Receive Signals
TD_M_C	11	8	A	Differential Transmit and Receive Signals
TD_P_D	13	10	A	Differential Transmit and Receive Signals
TD_M_D	14	11	A	Differential Transmit and Receive Signals
OTHER PINS
Reserved	1, 7, 9, 16		A	Reserved
RBIAS	15	12	A	Bias Resistor Connection. A 11 kΩ +/-1% resistor should be connected from RBIAS to GND.
POWER AND GROUND PINS
VDDIO	23, 41, 57	19, 30, 41	P	I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1µF & 0.1µF capacitor to GND
VDDA1P8	17, 64	13, 48	P	1.8V Analog Supply (+/-5%).
				No external supply is required for this pin. When unused, no connections should be made to this pin.
				For additional power savings, an external 1.8V supply can be connected to these pins. When using an external supply, each pin requires a 1µF & 0.1µF capacitor to GND.
VDDA2P5	4, 12	3, 9	P	2.5V Analog Supply (+/-5%). Each pin requires a 1µF & 0.1µF capacitor to GND
VDD1P1	8, 29, 42, 58		P	1.1V Analog Supply (+/-5%). Each pin requires a 1µF & 0.1µF capacitor to GND
VDD1P0		6, 24, 31, 42	P	1.0V Analog Supply (+15.5%,-5%). Each pin requires a 1µF & 0.1µF capacitor to GND
GND	Die Attach Pad	Die Attach Pad	P	Ground

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The functionalities of the pins are defined below.

Type I: Input
Type O: Output
Type I/O: Input /Output
Type PD or PU: Internal Pull-down or Pull-up
Type S: Strap Configuration Pin
Type: A Analog pins