JAJSC33 データシート

JAJSC33G February 2015 – October 2022 DP83867CR , DP83867IR

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

RGZ|48
PAP|64

サーマルパッド・メカニカル・データ

PAP|64
- PPTD078J
RGZ|48
- QFND014T

発注情報

7.9 RGMII Timing

See Figure 7-16 and .Figure 7-17

PARAMETER		TEST CONDITIONS⁽⁵⁾	MIN	NOM	MAX	UNIT
T_skewT	Data to Clock output Skew (at Transmitter)	See ⁽¹⁾	–500	0	500	ps
T_skewR	Data to Clock input Skew (at Receiver)	See ⁽¹⁾	1	1.8	2.6	ns
T_setupT	Data to Clock output Setup (at Transmitter – internal delay)	See ⁽⁴⁾	1.2	2		ns
T_holdT	Clock to Data output Hold (at Transmitter – internal delay)	See ⁽⁴⁾	1.2	2		ns
T_setupR	Data to Clock input Setup (at Reciever – internal delay)	See ⁽⁴⁾	1	2		ns
T_holdR	Clock to Data input Hold (at Receiver – internal delay)	See ⁽⁴⁾	1	2		ns
T_cyc	Clock Cycle Duration	See ⁽²⁾	7.2	8	8.8	ns
Duty_G	Duty Cycle for Gigabit	See ⁽³⁾⁽⁷⁾	45	50	55%
Duty_T	Duty Cycle for 10/100T	See ⁽³⁾⁽⁷⁾	40	50	60%
T_R	Rise Time (20% to 80%)				0.75	ns
T_F	Fall Time (20% to 80%)				0.75	ns
T_TXLAT	RGMII to MDI Latency	See ⁽⁶⁾		88		ns
T_RXLAT	MDI to RGMII Latency	See ⁽⁶⁾		288		ns

(1) When operating without RGMII internal delay, the PCB design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal.

(2) For 10-Mbps and 100-Mbps, Tcyc will scale to 400 ns ± 40 ns and 40 ns ± 4 ns.

(3) Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between.

(4) Device may operate with or without internal delay.

(5) Ensured by production test, characterization, or design.

(6) Operating in 1000Base-T .

(7) Duty cycle values are defined in percentages of the nominal clock speed. For example, the minimum Gigabit RGMII clock pulse duration is 45 % of 8 ns.