JAJSD08 データシート

JAJSD08D October 2015 – November 2022 DP83867CS , DP83867E , DP83867IS

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

RGZ|48

サーマルパッド・メカニカル・データ

RGZ|48
- QFND014T

発注情報

8.5.1 Strap Configuration

The DP83867 uses many of the functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap options are internally reloaded from the values sampled at power up or hard reset. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

The strap pins supported are 4-level straps, which are described in greater detail below.

Note:

Because strap pins may have alternate functions after reset is deasserted, they should not be connected directly to VDD or GND.

Configuration of the device may be done through the 4-level strap pins or through the management register interface. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the 4-level strap pin input and the supply to select one of the possible selected modes.

The MAC interface pins must support I/O voltages of 3.3 V, 2.5 V, and 1.8 V. As the strap inputs are implemented on these pins, the straps must also support operation at 3.3-V, 2.5-V, and 1.8-V supplies.

For more information about configuring 4-level straps, see the Configuring Ethernet Devices with 4-Level Straps application report (SNLA258).

Figure 8-10 Strap Circuit

Table 8-4 4-Level Strap Resistor Ratios

MODE	TARGET VOLTAGE			IDEAL Rhi (kΩ)	IDEAL Rlo (kΩ)
MODE	Vmin (V)	Vtyp (V)	Vmax (V)	IDEAL Rhi (kΩ)	IDEAL Rlo (kΩ)
1	0	0	0.098 × VDDIO	OPEN	OPEN
2	0.140 × VDDIO	0.165 × VDDIO	0.191 × VDDIO	10	2.49
3	0.225 × VDDIO	0.255 × VDDIO	0.284 × VDDIO	5.76	2.49
4	0.694 × VDDIO	0.783 × VDDIO	0.888 × VDDIO	2.49	OPEN

For SGMII Mode 4 strap, TI recommends using Rhi = 4 kΩ and Rlo = 10 kΩ on RX_D0 and RX_D1 , RX_D2 and RX_D3.

All straps have a 9 kΩ ±25% internal pulldown resistor. The voltage at strap pins should be between the Vmin and Vmax mentioned in the Target Voltage column in Table 8-4. Strap resistors with 1% tolerance are recommended.

The following tables describes the DP83867 configuration straps:

Table 8-5 4-Level Strap Pins

PIN NAME	48 VQFN PIN #	DEFAULT	STRAP FUNCTION
RX_D0	33	[00]	MODE	PHY_ADD1	PHY_ADD0
			1	0	0
			2	0	1
			3	1	0
			4	1	1
RX_D2	35	[00]	MODE	PHY_ADD3	PHY_ADD2
			1	0	0
			2	0	1
			3	1	0
			4	1	1
RX_CTRL ⁽¹⁾	38	[00]	MODE		Autoneg Disable
			1		N/A
			2		N/A
			3		0
			4		1
GPIO_0 ⁽²⁾	39	[00]	MODE	RGMII Clock Skew RX[0]
			1	0
			2	Not Applicable
			3	1
			4	Not Applicable
GPIO_1	40	[00]	MODE	RGMII Clock Skew RX[2]	RGMII Clock Skew RX[1]
			1	0	0
			2	0	1
			3	1	0
			4	1	1
LED_2	45	[00]	MODE	RGMII Clock Skew TX[1]	RGMII Clock Skew TX[0]
			1	0	0
			2	0	1
			3	1	0
			4	1	1
LED_1	46	[00]	MODE	ANEG_SEL	RGMII Clock Skew TX[2]
			1	0	0
			2	0	1
			3	1	0
			4	1	1
LED_0	47	[00]	MODE	Mirror Enable	SGMII Enable
			1	0	0
			2	0	1
			3	1	0
			4	1	1

(1) Strap modes 1 and 2 are not applicable for RX_CTRL. The RX_CTRL strap must be configured for strap mode 3 or strap mode 4. If the RX_CTRL pin cannot be strapped to mode 3 or mode 4, bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. Autoneg Disable should always be set to 0 when using gigabit Ethernet.

(2) Only Mode 1 and 3 are valid for GPIO_0. Mode 2 and 4 are not applicable and should not be used.

Note:

RX_D1 is not a strap input, but this pin must be populated with the same strap resistors chosen for RX_D0. RX_D0 and RX_D1 form an SGMII differential pair. The dummy straps on RX_D1 are required to provide a balanced load for this SGMII differential pair.

Note:

RX_D3 is not a strap input, but this pin must be populated with the same strap resistors chosen for RX_D2. RX_D2 and RX_D3 form an SGMII differential pair. The dummy straps on RX_D3 are required to provide a balanced load for this SGMII differential pair.

Table 8-6 Auto-Negotiation Select Strap Details

MODE	ANEG_SEL	REMARKS
10/100/1000	0	advertise ability of 10/100/1000
100/1000	1	advertise ability of 100/1000 only

Table 8-7 RGMII Transmit Clock Skew Details

MODE	RGMII CLOCK SKEW TX[2]	RGMII CLOCK SKEW TX[1]	RGMII CLOCK SKEW TX[0]	RGMII TX CLOCK SKEW
1	0	0	0	2.0 ns
2	0	0	1	1.5 ns
3	0	1	0	1.0 ns
4	0	1	1	0.5 ns
5	1	0	0	0 ns
6	1	0	1	3.5 ns
7	1	1	0	3.0 ns
8	1	1	1	2.5 ns

Table 8-8 RGMII Receive Clock Skew Details

MODE	RGMII CLOCK SKEW RX[2]	RGMII CLOCK SKEW RX[1]	RGMII CLOCK SKEW RX[0]	RGMII RX CLOCK SKEW
1	0	0	0	2.0 ns
2	0	0	1	1.5 ns
3	0	1	0	1.0 ns
4	0	1	1	0.5 ns
5	1	0	0	0 ns
6	1	0	1	3.5 ns
7	1	1	0	3.0 ns
8	1	1	1	2.5 ns