JAJSF32A November 2017 – March 2018 DP83TC811R-Q1
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Receive Error Counter | |||||||
RO/COR-0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Receive Error Counter | |||||||
RO/COR-0 |
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
15:0 | Receive Error Counter | RO, COR | 0 | RX_ER Counter:
When a valid carrier is presented (only while RX_DV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in xMII loopback mode. The counter stops when it reaches its maximum count (0xFFFF). When the counter exceeds half-full (0x7FFF), an interrupt is generated. This register is cleared on read. |