JAJSF32A
November 2017 – March 2018
DP83TC811R-Q1
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
概略回路図
4
改訂履歴
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
6.1
Pin Multiplexing
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Timing Diagrams
7.8
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Wake-on-LAN (WoL) Packet Detection
8.3.1.1
Magic Packet Structure
8.3.1.2
Magic Packet Example
8.3.1.3
Wake-on-LAN Configuration and Status
8.3.2
Start of Frame Detect for IEEE 1588 Time Stamp
8.3.3
Diagnostic Tool Kit
8.3.3.1
Signal Quality Indicator
8.3.3.2
Electrostatic Discharge Sensing
8.3.3.3
Time Domain Reflectometry
8.3.3.4
Temperature and Voltage Sensing
8.3.3.5
Built-In Self-Test
8.3.3.6
Loopback Modes
8.3.3.6.1
xMII Loopback
8.3.3.6.2
PCS Loopback
8.3.3.6.3
Analog Loopback
8.3.3.6.4
Reverse Loopback
8.3.4
Compliance Test Modes
8.3.4.1
Test Mode 1
8.3.4.2
Test Mode 2
8.3.4.3
Test Mode 4
8.3.4.4
Test Mode 5
8.4
Device Functional Modes
8.4.1
Power Down
8.4.2
Reset
8.4.3
Disable
8.4.4
Standby
8.4.5
Normal
8.4.6
Sleep Request
8.4.7
Silent
8.4.8
Sleep
8.4.9
Low-Power Sleep
8.4.10
Wake-Up
8.4.11
State Transitions
8.4.11.1
State Transition #1 - Standby to Normal
8.4.11.2
State Transition #2 - Normal to Standby
8.4.11.3
State Transition #3 - Normal to Sleep Request
8.4.11.4
State Transition #4 - Sleep Request to Normal
8.4.11.5
State Transition #5 - Sleep Request to Standby
8.4.11.6
State Transition #6 - Sleep Request to Silent
8.4.11.7
State Transition #7 - Silent to Standby
8.4.11.8
State Transition #8 - Silent to Sleep
8.4.12
Media Dependent Interface
8.4.12.1
100BASE-T1 Master and 100BASE-T1 Slave Configuration
8.4.12.2
Auto-Polarity Detection and Correction
8.4.12.3
Jabber Detection
8.4.12.4
Interleave Detection
8.4.13
MAC Interfaces
8.4.13.1
Media Independent Interface
8.4.13.2
Reduced Media Independent Interface
8.4.13.3
Reduced Gigabit Media Independent Interface
8.4.14
Serial Management Interface
8.4.15
Direct Register Access
8.4.16
Extended Register Space Access
8.4.17
Write Address Operation
8.4.17.1
MMD1 - Write Address Operation
8.4.18
Read Address Operation
8.4.18.1
MMD1 - Read Address Operation
8.4.19
Write Operation (No Post Increment)
8.4.19.1
MMD1 - Write Operation (No Post Increment)
8.4.20
Read Operation (No Post Increment)
8.4.20.1
MMD1 - Read Operation (No Post Increment)
8.4.21
Write Operation (Post Increment)
8.4.21.1
MMD1 - Write Operation (Post Increment)
8.4.22
Read Operation (Post Increment)
8.4.22.1
MMD1 - Read Operation (Post Increment)
8.5
Programming
8.5.1
Strap Configuration
8.5.2
LED Configuration
8.5.3
PHY Address Configuration
8.6
Register Maps
8.6.1
Register Access Summary
8.6.2
BMCR Register 0x0000 – Basic Mode Control Register
Table 25.
BMCR Field Descriptions
8.6.3
BMSR Register 0x0001 – Basic Mode Status Register
Table 26.
BMSR Field Descriptions
8.6.4
PHYID1 Register 0x0002 – PHY Identifier Register #1
Table 27.
PHYID1 Field Descriptions
8.6.5
PHYID2 Register 0x0003 – PHY Identifier Register #2
Table 28.
PHYID2 Field Descriptions
8.6.6
TDR_AUTO Register 0x0009 – TDR Auto-Run Register
Table 29.
TDR_AUTO Field Descriptions
8.6.7
REGCR Register 0x000D – Register Control Register
Table 30.
REGCR Field Descriptions
8.6.8
ADDAR Register 0x000E – Address/Data Register
Table 31.
ADDAR Field Descriptions
8.6.9
INT_TEST Register 0x0011 – Interrupt Test Register
Table 32.
INT_TEST Field Descriptions
8.6.10
INT_STAT1 Register 0x0012 – Interrupt Status Register #1
Table 33.
INT_STAT1 Field Descriptions
8.6.11
INT_STAT2 Register 0x0013 – Interrupt Status Register #2
Table 34.
INT_STAT2 Field Descriptions
8.6.12
FCSCR Register 0x0014 – False Carrier Sense Counter Register
Table 35.
FCSCR Field Descriptions
8.6.13
RECR Register 0x0015 – Receive Error Count Register
Table 36.
RECR Field Descriptions
8.6.14
BISTCR Register 0x0016 – BIST Control Register
Table 37.
BISTCR Field Descriptions
8.6.15
xMII_CTRL Register 0x0017 – xMII Control Register
Table 38.
xMII_CTRL Field Descriptions
8.6.16
INT_STAT3 Register 0x0018 – Interrupt Status Register #3
Table 39.
INT_STAT3 Field Descriptions
8.6.17
BICTSR1 Register 0x001B – BIST Control and Status Register #1
Table 40.
BICTSR1 Field Descriptions
8.6.18
BICTSR2 Register 0x001C – BIST Control and Status Register #2
Table 41.
BICTSR2 Field Description
8.6.19
TDR Register 0x001E – Time Domain Reflectometry Register
Table 42.
TDR Field Descriptions
8.6.20
PHYRCR Register 0x001F – PHY Reset Control Register
Table 43.
PHYRCR Field Descriptions
8.6.21
LSR Register 0x0133 – Link Status Results Register
Table 44.
LSR Field Descriptions
8.6.22
TDRR Register 0x016B – TDR Results Register
Table 45.
TDRR Field Descriptions
8.6.23
TDRLR1 Register 0x0180 – TDR Location Result Register #1
Table 46.
TDRLR1 Field Descriptions
8.6.24
TDRLR2 Register 0x0181 – TDR Location Result Register #2
Table 47.
TDRLR2 Field Descriptions
8.6.25
TDRPT Register 0x018A – TDR Peak Type Register
Table 48.
TDRPT Field Descriptions
8.6.26
AUTO_PHY Register 0x018B – Autonomous PHY Control Register
Table 49.
AUTO_PHY Field Descriptions
8.6.27
PWRM Register 0x018C – Power Mode Register
Table 50.
PWRM Register 0x018C – Power Mode Register
8.6.28
SNR Register 0x0197 – Signal-to-Noise Ratio Result Register
Table 51.
SNR Field Descriptions
8.6.29
SQI Register 0x0198 – Signal Quality Indication Register
Table 52.
SQI Field Descriptions
8.6.30
LD_CTRL Register 0x0400 – Line Driver Control Register
Table 53.
LD_CTRL Field Descriptions
8.6.31
LDG_CTRL1 Register 0x0401 – Line Driver Gain Control Register #1
Table 54.
LDG_CTRL1 Field Descriptions
8.6.32
LDG_CTRL2 Register 0x0402 – Line Driver Control Register #2
Table 55.
LDG_CTRL1 Field Descriptions
8.6.33
DLL_CTRL 0x0446 – RGMII DLL Control Register
Table 56.
DLL_CTRL Field Descriptions
8.6.34
ESDS Register 0x0448 – Electrostatic Discharge Status Register
Table 57.
ESDS Field Descriptions
8.6.35
LED_CFG1 Register 0x0460 – LED Configuration Register #1
Table 58.
LED_CFG1 Field Descriptions
8.6.36
xMII_IMP_CTRL Register 0x0461 – xMII Impedance Control Register
Table 59.
xMII_IMP_CTRL Field Descriptions
8.6.37
IO_CTRL1 Register 0x0462 – GPIO Control Register #1
Table 60.
IO_CTRL1 Field Descriptions
8.6.38
IO_CTRL2 Register 0x0463 – GPIO Control Register #2
Table 61.
IO_CTRL2 Field Descriptions
8.6.39
STRAP Register 0x0467 – Strap Configuration Register
Table 62.
STRAP Field Descriptions
8.6.40
LED_CFG2 Register 0x0469 – LED Configuration Register #2
Table 63.
LED_CFG2 Field Descriptions
8.6.41
MON_CFG1 Register 0x0480 – Monitor Configuration Register #1
Table 64.
MON_CFG1 Field Descriptions
8.6.42
MON_CFG2 Register 0x0481 – Monitor Configuration Register #2
Table 65.
MON_CFG2 Field Descriptions
8.6.43
MON_CFG3 Register 0x0482 – Monitor Configuration Register #3
Table 66.
MON_CFG3 Field Descriptions
8.6.44
MON_STAT1 Register 0x0483 – Monitor Status Register #1
Table 67.
MON_STAT1 Field Descriptions
8.6.45
MON_STAT2 Register 0x0484 – Monitor Status Register #2
Table 68.
MON_STAT2 Field Descriptions
8.6.46
PCS_CTRL1 Register 0x0485 – PCS Control Register #1
Table 69.
PCS_CTRL1 Field Descriptions
8.6.47
PCS_CTRL2 Register – 0x0486 PCS Control Register #2
Table 70.
PCS_CTRL2 Field Descriptions
8.6.48
LPS_CTRL2 Register 0x0487 – LPS Control Register #2
Table 71.
LPS_CTRL2 Register 0x0487 – LPS Control Register #2
8.6.49
INTER_CFG Register 0x0489 – Interleave Configuration
Table 72.
INTER_CFG Field Descriptions
8.6.50
LPS_CTRL3 Register 0x0493 – LPS Control Register #3
Table 73.
LPS_CTRL3 Register 0x0493 – LPS Control Register #3
8.6.51
JAB_CFG Register 0x0496 – Jabber Configuration Register
Table 74.
JAB_CFG Field Descriptions
8.6.52
TEST_MODE_CTRL Register 0x0497 – Test Mode Control Register
Table 75.
TEST_MODE_CTRL Field Descriptions
8.6.53
WOL_CFG Register 0x04A0 – WoL Configuration Register
Table 76.
WOL_CFG Field Descriptions
8.6.54
WOL_STAT Register 0x04A1 – WoL Status Register
Table 77.
WOL_STAT Field Descriptions
8.6.55
WOL_DA1 Register 0x04A2 – WoL Destination Address Configuration Register #1
Table 78.
WOL_DA1 Field Descriptions
8.6.56
WOL_DA2 Register 0x04A3 – WoL Destination Address Configuration Register #2
Table 79.
WOL_DA2 Field Descriptions
8.6.57
WOL_DA3 Register 0x04A4 – WoL Destination Address Configuration Register #3
Table 80.
WOL_DA3 Field Descriptions
8.6.58
RXSOP1 Register 0x04A5 – Receive Secure-ON Password Register #1
Table 81.
RXSOP1 Field Descriptions
8.6.59
RXSOP2 Register 0x04A6 – Receive Secure-ON Password Register #2
Table 82.
RXSOP2 Field Descriptions
8.6.60
RXSOP3 Register 0x04A7 – Receive Secure-ON Password Register #3
Table 83.
RXSOP3 Field Descriptions
8.6.61
RXPAT1 Register 0x04A8 – Receive Pattern Register #1
Table 84.
RXPAT1 Field Descriptions
8.6.62
RXPAT2 Register 0x04A9 – Receive Pattern Register #2
Table 85.
RXPAT2 Field Descriptions
8.6.63
RXPAT3 Register 0x04AA – Receive Pattern Register #3
Table 86.
RXPAT3 Field Descriptions
8.6.64
RXPAT4 Register 0x04AB – Receive Pattern Register #4
Table 87.
RXPAT4 Field Descriptions
8.6.65
RXPAT5 Register 0x04AC – Receive Pattern Register #5
Table 88.
RXPAT5 Field Descriptions
8.6.66
RXPAT6 Register 0x04AD – Receive Pattern Register #6
Table 89.
RXPAT6 Field Descriptions
8.6.67
RXPAT7 Register 0x04AE – Receive Pattern Register #7
Table 90.
RXPAT7 Field Descriptions
8.6.68
RXPAT8 Register 0x04AF – Receive Pattern Register #8
Table 91.
RXPAT8 Field Descriptions
8.6.69
RXPAT9 Register 0x04B0 – Receive Pattern Register #9
Table 92.
RXPAT9 Field Descriptions
8.6.70
RXPAT10 Register 0x04B1 – Receive Pattern Register #10
Table 93.
RXPAT10 Field Descriptions
8.6.71
RXPAT11 Register 0x04B2 Receive Pattern Register #11
Table 94.
RXPAT11 Field Descriptions
8.6.72
RXPAT12 Register 0x04B3 – Receive Pattern Register #12
Table 95.
RXPAT12 Field Descriptions
8.6.73
RXPAT13 Register 0x04B4 – Receive Pattern Register #13
Table 96.
RXPAT13 Field Descriptions
8.6.74
RXPAT14 Register 0x04B5 – Receive Pattern Register #14
Table 97.
RXPAT14 Field Descriptions
8.6.75
RXPAT15 Register 0x04B6 – Receive Pattern Register #15
Table 98.
RXPAT15 Field Descriptions
8.6.76
RXPAT16 Register 0x04B7 – Receive Pattern Register #16
Table 99.
RXPAT16 Field Descriptions
8.6.77
RXPAT17 Register 0x04B8 – Receive Pattern Register #17
Table 100.
RXPAT17 Field Descriptions
8.6.78
RXPAT18 Register 0x04B9 – Receive Pattern Register #18
Table 101.
RXPAT18 Field Descriptions
8.6.79
RXPAT19 Register 0x04BA Receive Pattern Register #19
Table 102.
RXPAT19 Field Descriptions
8.6.80
RXPAT20 Register 0x04BB – Receive Pattern Register #20
Table 103.
RXPAT20 Field Descriptions
8.6.81
RXPAT21 Register 0x04BC – Receive Pattern Register #21
Table 104.
RXPAT21 Field Descriptions
8.6.82
RXPAT22 Register 0x04BD – Receive Pattern Register #22
Table 105.
RXPAT22 Field Descriptions
8.6.83
RXPAT23 Register 0x04BE – Receive Pattern Register #23
Table 106.
RXPAT23 Field Descriptions
8.6.84
RXPAT24 Register 0x04BF – Receive Pattern Register #24
Table 107.
RXPAT24 Field Descriptions
8.6.85
RXPAT25 Register 0x04C0 – Receive Pattern Register #25
Table 108.
RXPAT25 Field Descriptions
8.6.86
RXPAT26 Register 0x04C1 – Receive Pattern Register #26
Table 109.
RXPAT26 Field Descriptions
8.6.87
RXPAT27 Register 0x04C2 Receive Pattern Register #27
Table 110.
RXPAT27 Field Descriptions
8.6.88
RXPAT28 Register 0x04C3 – Receive Pattern Register #28
Table 111.
RXPAT28 Field Descriptions
8.6.89
RXPAT29 Register 0x04C4 – Receive Pattern Register #29
Table 112.
RXPAT29 Field Descriptions
8.6.90
RXPAT30 Register 0x04C5 – Receive Pattern Register #30
Table 113.
RXPAT30 Field Descriptions
8.6.91
RXPAT31 Register 0x04C6 – Receive Pattern Register #31
Table 114.
RXPAT31 Field Descriptions
8.6.92
RXPAT32 Register 0x04C7 – Receive Pattern Register #32
Table 115.
RXPAT32 Field Descriptions
8.6.93
RXPBM1 Register 0x04C8 – Receive Pattern Byte Mask Register #1
Table 116.
RXPBM1 Field Descriptions
8.6.94
RXPBM2 Register 0x04C9 – Receive Pattern Byte Mask Register #2
Table 117.
RXPBM2 Field Descriptions
8.6.95
RXPBM3 Register 0x04CA – Receive Pattern Byte Mask Register #3
Table 118.
RXPBM3 Field Descriptions
8.6.96
RXPBM4 Register 0x04CB – Receive Pattern Byte Mask Register #4
Table 119.
RXPBM4 Field Descriptions
8.6.97
RXPATC Register 0x04CC – Receive Pattern Control Register
Table 120.
RXPATC Field Descriptions
8.6.98
RXD3CLK Register 0x04E0 – RX_D3 Clock Control Register
Table 121.
RXD3CLK Field Descriptions
8.6.99
LPS_CFG Register 0x04E5 – LPS Configuration Register
Table 122.
LPS_CFG Register 0x04E5 – LPS Configuration Register
8.6.100
PMA_CTRL1 Register 0x0007 – MMD1 PMA Control Register #1
Table 123.
PMA_CTRL1 Field Descriptions
8.6.101
PMA_EXT1 Register 0x000B – MMD1 PMA Extended Ability Register #1
Table 124.
PMA_EXT1 Field Descriptions
8.6.102
PMA_EXT2 Register 0x0012 – MMD1 PMA Extended Ability Register #2
Table 125.
PMA_EXT2 Field Descriptions
8.6.103
PMA_CTRL2 Register 0x0834 – MMD1 PMA Control Register #2
Table 126.
PMA_CTRL2 Field Descriptions
8.6.104
TEST_CTRL Register 0x0836 – MMD1 100BASE-T1 PMA Test Control Register
Table 127.
TEST_CTRL Field Descriptions
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Design Requirements
9.2.1.1
Physical Medium Attachment
9.2.1.1.1
Common-Mode Choke Recommendations
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Signal Traces
11.1.2
Return Path
11.1.3
Metal Pour
11.1.4
PCB Layer Stacking
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントの更新通知を受け取る方法
12.2
コミュニティ・リソース
12.3
商標
12.4
静電気放電に関する注意事項
12.5
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
RND|36
MPQF428
サーマルパッド・メカニカル・データ
発注情報
jajsf32a_oa
jajsf32a_pm
8.4.12
Media Dependent Interface