JAJSF32A November   2017  – March 2018 DP83TC811R-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Pin Multiplexing
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Wake-on-LAN (WoL) Packet Detection
        1. 8.3.1.1 Magic Packet Structure
        2. 8.3.1.2 Magic Packet Example
        3. 8.3.1.3 Wake-on-LAN Configuration and Status
      2. 8.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
      3. 8.3.3 Diagnostic Tool Kit
        1. 8.3.3.1 Signal Quality Indicator
        2. 8.3.3.2 Electrostatic Discharge Sensing
        3. 8.3.3.3 Time Domain Reflectometry
        4. 8.3.3.4 Temperature and Voltage Sensing
        5. 8.3.3.5 Built-In Self-Test
        6. 8.3.3.6 Loopback Modes
          1. 8.3.3.6.1 xMII Loopback
          2. 8.3.3.6.2 PCS Loopback
          3. 8.3.3.6.3 Analog Loopback
          4. 8.3.3.6.4 Reverse Loopback
      4. 8.3.4 Compliance Test Modes
        1. 8.3.4.1 Test Mode 1
        2. 8.3.4.2 Test Mode 2
        3. 8.3.4.3 Test Mode 4
        4. 8.3.4.4 Test Mode 5
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Down
      2. 8.4.2  Reset
      3. 8.4.3  Disable
      4. 8.4.4  Standby
      5. 8.4.5  Normal
      6. 8.4.6  Sleep Request
      7. 8.4.7  Silent
      8. 8.4.8  Sleep
      9. 8.4.9  Low-Power Sleep
      10. 8.4.10 Wake-Up
      11. 8.4.11 State Transitions
        1. 8.4.11.1 State Transition #1 - Standby to Normal
        2. 8.4.11.2 State Transition #2 - Normal to Standby
        3. 8.4.11.3 State Transition #3 - Normal to Sleep Request
        4. 8.4.11.4 State Transition #4 - Sleep Request to Normal
        5. 8.4.11.5 State Transition #5 - Sleep Request to Standby
        6. 8.4.11.6 State Transition #6 - Sleep Request to Silent
        7. 8.4.11.7 State Transition #7 - Silent to Standby
        8. 8.4.11.8 State Transition #8 - Silent to Sleep
      12. 8.4.12 Media Dependent Interface
        1. 8.4.12.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 8.4.12.2 Auto-Polarity Detection and Correction
        3. 8.4.12.3 Jabber Detection
        4. 8.4.12.4 Interleave Detection
      13. 8.4.13 MAC Interfaces
        1. 8.4.13.1 Media Independent Interface
        2. 8.4.13.2 Reduced Media Independent Interface
        3. 8.4.13.3 Reduced Gigabit Media Independent Interface
      14. 8.4.14 Serial Management Interface
      15. 8.4.15 Direct Register Access
      16. 8.4.16 Extended Register Space Access
      17. 8.4.17 Write Address Operation
        1. 8.4.17.1 MMD1 - Write Address Operation
      18. 8.4.18 Read Address Operation
        1. 8.4.18.1 MMD1 - Read Address Operation
      19. 8.4.19 Write Operation (No Post Increment)
        1. 8.4.19.1 MMD1 - Write Operation (No Post Increment)
      20. 8.4.20 Read Operation (No Post Increment)
        1. 8.4.20.1 MMD1 - Read Operation (No Post Increment)
      21. 8.4.21 Write Operation (Post Increment)
        1. 8.4.21.1 MMD1 - Write Operation (Post Increment)
      22. 8.4.22 Read Operation (Post Increment)
        1. 8.4.22.1 MMD1 - Read Operation (Post Increment)
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1   Register Access Summary
      2. 8.6.2   BMCR Register 0x0000 – Basic Mode Control Register
        1. Table 25. BMCR Field Descriptions
      3. 8.6.3   BMSR Register 0x0001 – Basic Mode Status Register
        1. Table 26. BMSR Field Descriptions
      4. 8.6.4   PHYID1 Register 0x0002 – PHY Identifier Register #1
        1. Table 27. PHYID1 Field Descriptions
      5. 8.6.5   PHYID2 Register 0x0003 – PHY Identifier Register #2
        1. Table 28. PHYID2 Field Descriptions
      6. 8.6.6   TDR_AUTO Register 0x0009 – TDR Auto-Run Register
        1. Table 29. TDR_AUTO Field Descriptions
      7. 8.6.7   REGCR Register 0x000D – Register Control Register
        1. Table 30. REGCR Field Descriptions
      8. 8.6.8   ADDAR Register 0x000E – Address/Data Register
        1. Table 31. ADDAR Field Descriptions
      9. 8.6.9   INT_TEST Register 0x0011 – Interrupt Test Register
        1. Table 32. INT_TEST Field Descriptions
      10. 8.6.10  INT_STAT1 Register 0x0012 – Interrupt Status Register #1
        1. Table 33. INT_STAT1 Field Descriptions
      11. 8.6.11  INT_STAT2 Register 0x0013 – Interrupt Status Register #2
        1. Table 34. INT_STAT2 Field Descriptions
      12. 8.6.12  FCSCR Register 0x0014 – False Carrier Sense Counter Register
        1. Table 35. FCSCR Field Descriptions
      13. 8.6.13  RECR Register 0x0015 – Receive Error Count Register
        1. Table 36. RECR Field Descriptions
      14. 8.6.14  BISTCR Register 0x0016 – BIST Control Register
        1. Table 37. BISTCR Field Descriptions
      15. 8.6.15  xMII_CTRL Register 0x0017 – xMII Control Register
        1. Table 38. xMII_CTRL Field Descriptions
      16. 8.6.16  INT_STAT3 Register 0x0018 – Interrupt Status Register #3
        1. Table 39. INT_STAT3 Field Descriptions
      17. 8.6.17  BICTSR1 Register 0x001B – BIST Control and Status Register #1
        1. Table 40. BICTSR1 Field Descriptions
      18. 8.6.18  BICTSR2 Register 0x001C – BIST Control and Status Register #2
        1. Table 41. BICTSR2 Field Description
      19. 8.6.19  TDR Register 0x001E – Time Domain Reflectometry Register
        1. Table 42. TDR Field Descriptions
      20. 8.6.20  PHYRCR Register 0x001F – PHY Reset Control Register
        1. Table 43. PHYRCR Field Descriptions
      21. 8.6.21  LSR Register 0x0133 – Link Status Results Register
        1. Table 44. LSR Field Descriptions
      22. 8.6.22  TDRR Register 0x016B – TDR Results Register
        1. Table 45. TDRR Field Descriptions
      23. 8.6.23  TDRLR1 Register 0x0180 – TDR Location Result Register #1
        1. Table 46. TDRLR1 Field Descriptions
      24. 8.6.24  TDRLR2 Register 0x0181 – TDR Location Result Register #2
        1. Table 47. TDRLR2 Field Descriptions
      25. 8.6.25  TDRPT Register 0x018A – TDR Peak Type Register
        1. Table 48. TDRPT Field Descriptions
      26. 8.6.26  AUTO_PHY Register 0x018B – Autonomous PHY Control Register
        1. Table 49. AUTO_PHY Field Descriptions
      27. 8.6.27  PWRM Register 0x018C – Power Mode Register
        1. Table 50. PWRM Register 0x018C – Power Mode Register
      28. 8.6.28  SNR Register 0x0197 – Signal-to-Noise Ratio Result Register
        1. Table 51. SNR Field Descriptions
      29. 8.6.29  SQI Register 0x0198 – Signal Quality Indication Register
        1. Table 52. SQI Field Descriptions
      30. 8.6.30  LD_CTRL Register 0x0400 – Line Driver Control Register
        1. Table 53. LD_CTRL Field Descriptions
      31. 8.6.31  LDG_CTRL1 Register 0x0401 – Line Driver Gain Control Register #1
        1. Table 54. LDG_CTRL1 Field Descriptions
      32. 8.6.32  LDG_CTRL2 Register 0x0402 – Line Driver Control Register #2
        1. Table 55. LDG_CTRL1 Field Descriptions
      33. 8.6.33  DLL_CTRL 0x0446 – RGMII DLL Control Register
        1. Table 56. DLL_CTRL Field Descriptions
      34. 8.6.34  ESDS Register 0x0448 – Electrostatic Discharge Status Register
        1. Table 57. ESDS Field Descriptions
      35. 8.6.35  LED_CFG1 Register 0x0460 – LED Configuration Register #1
        1. Table 58. LED_CFG1 Field Descriptions
      36. 8.6.36  xMII_IMP_CTRL Register 0x0461 – xMII Impedance Control Register
        1. Table 59. xMII_IMP_CTRL Field Descriptions
      37. 8.6.37  IO_CTRL1 Register 0x0462 – GPIO Control Register #1
        1. Table 60. IO_CTRL1 Field Descriptions
      38. 8.6.38  IO_CTRL2 Register 0x0463 – GPIO Control Register #2
        1. Table 61. IO_CTRL2 Field Descriptions
      39. 8.6.39  STRAP Register 0x0467 – Strap Configuration Register
        1. Table 62. STRAP Field Descriptions
      40. 8.6.40  LED_CFG2 Register 0x0469 – LED Configuration Register #2
        1. Table 63. LED_CFG2 Field Descriptions
      41. 8.6.41  MON_CFG1 Register 0x0480 – Monitor Configuration Register #1
        1. Table 64. MON_CFG1 Field Descriptions
      42. 8.6.42  MON_CFG2 Register 0x0481 – Monitor Configuration Register #2
        1. Table 65. MON_CFG2 Field Descriptions
      43. 8.6.43  MON_CFG3 Register 0x0482 – Monitor Configuration Register #3
        1. Table 66. MON_CFG3 Field Descriptions
      44. 8.6.44  MON_STAT1 Register 0x0483 – Monitor Status Register #1
        1. Table 67. MON_STAT1 Field Descriptions
      45. 8.6.45  MON_STAT2 Register 0x0484 – Monitor Status Register #2
        1. Table 68. MON_STAT2 Field Descriptions
      46. 8.6.46  PCS_CTRL1 Register 0x0485 – PCS Control Register #1
        1. Table 69. PCS_CTRL1 Field Descriptions
      47. 8.6.47  PCS_CTRL2 Register – 0x0486 PCS Control Register #2
        1. Table 70. PCS_CTRL2 Field Descriptions
      48. 8.6.48  LPS_CTRL2 Register 0x0487 – LPS Control Register #2
        1. Table 71. LPS_CTRL2 Register 0x0487 – LPS Control Register #2
      49. 8.6.49  INTER_CFG Register 0x0489 – Interleave Configuration
        1. Table 72. INTER_CFG Field Descriptions
      50. 8.6.50  LPS_CTRL3 Register 0x0493 – LPS Control Register #3
        1. Table 73. LPS_CTRL3 Register 0x0493 – LPS Control Register #3
      51. 8.6.51  JAB_CFG Register 0x0496 – Jabber Configuration Register
        1. Table 74. JAB_CFG Field Descriptions
      52. 8.6.52  TEST_MODE_CTRL Register 0x0497 – Test Mode Control Register
        1. Table 75. TEST_MODE_CTRL Field Descriptions
      53. 8.6.53  WOL_CFG Register 0x04A0 – WoL Configuration Register
        1. Table 76. WOL_CFG Field Descriptions
      54. 8.6.54  WOL_STAT Register 0x04A1 – WoL Status Register
        1. Table 77. WOL_STAT Field Descriptions
      55. 8.6.55  WOL_DA1 Register 0x04A2 – WoL Destination Address Configuration Register #1
        1. Table 78. WOL_DA1 Field Descriptions
      56. 8.6.56  WOL_DA2 Register 0x04A3 – WoL Destination Address Configuration Register #2
        1. Table 79. WOL_DA2 Field Descriptions
      57. 8.6.57  WOL_DA3 Register 0x04A4 – WoL Destination Address Configuration Register #3
        1. Table 80. WOL_DA3 Field Descriptions
      58. 8.6.58  RXSOP1 Register 0x04A5 – Receive Secure-ON Password Register #1
        1. Table 81. RXSOP1 Field Descriptions
      59. 8.6.59  RXSOP2 Register 0x04A6 – Receive Secure-ON Password Register #2
        1. Table 82. RXSOP2 Field Descriptions
      60. 8.6.60  RXSOP3 Register 0x04A7 – Receive Secure-ON Password Register #3
        1. Table 83. RXSOP3 Field Descriptions
      61. 8.6.61  RXPAT1 Register 0x04A8 – Receive Pattern Register #1
        1. Table 84. RXPAT1 Field Descriptions
      62. 8.6.62  RXPAT2 Register 0x04A9 – Receive Pattern Register #2
        1. Table 85. RXPAT2 Field Descriptions
      63. 8.6.63  RXPAT3 Register 0x04AA – Receive Pattern Register #3
        1. Table 86. RXPAT3 Field Descriptions
      64. 8.6.64  RXPAT4 Register 0x04AB – Receive Pattern Register #4
        1. Table 87. RXPAT4 Field Descriptions
      65. 8.6.65  RXPAT5 Register 0x04AC – Receive Pattern Register #5
        1. Table 88. RXPAT5 Field Descriptions
      66. 8.6.66  RXPAT6 Register 0x04AD – Receive Pattern Register #6
        1. Table 89. RXPAT6 Field Descriptions
      67. 8.6.67  RXPAT7 Register 0x04AE – Receive Pattern Register #7
        1. Table 90. RXPAT7 Field Descriptions
      68. 8.6.68  RXPAT8 Register 0x04AF – Receive Pattern Register #8
        1. Table 91. RXPAT8 Field Descriptions
      69. 8.6.69  RXPAT9 Register 0x04B0 – Receive Pattern Register #9
        1. Table 92. RXPAT9 Field Descriptions
      70. 8.6.70  RXPAT10 Register 0x04B1 – Receive Pattern Register #10
        1. Table 93. RXPAT10 Field Descriptions
      71. 8.6.71  RXPAT11 Register 0x04B2 Receive Pattern Register #11
        1. Table 94. RXPAT11 Field Descriptions
      72. 8.6.72  RXPAT12 Register 0x04B3 – Receive Pattern Register #12
        1. Table 95. RXPAT12 Field Descriptions
      73. 8.6.73  RXPAT13 Register 0x04B4 – Receive Pattern Register #13
        1. Table 96. RXPAT13 Field Descriptions
      74. 8.6.74  RXPAT14 Register 0x04B5 – Receive Pattern Register #14
        1. Table 97. RXPAT14 Field Descriptions
      75. 8.6.75  RXPAT15 Register 0x04B6 – Receive Pattern Register #15
        1. Table 98. RXPAT15 Field Descriptions
      76. 8.6.76  RXPAT16 Register 0x04B7 – Receive Pattern Register #16
        1. Table 99. RXPAT16 Field Descriptions
      77. 8.6.77  RXPAT17 Register 0x04B8 – Receive Pattern Register #17
        1. Table 100. RXPAT17 Field Descriptions
      78. 8.6.78  RXPAT18 Register 0x04B9 – Receive Pattern Register #18
        1. Table 101. RXPAT18 Field Descriptions
      79. 8.6.79  RXPAT19 Register 0x04BA Receive Pattern Register #19
        1. Table 102. RXPAT19 Field Descriptions
      80. 8.6.80  RXPAT20 Register 0x04BB – Receive Pattern Register #20
        1. Table 103. RXPAT20 Field Descriptions
      81. 8.6.81  RXPAT21 Register 0x04BC – Receive Pattern Register #21
        1. Table 104. RXPAT21 Field Descriptions
      82. 8.6.82  RXPAT22 Register 0x04BD – Receive Pattern Register #22
        1. Table 105. RXPAT22 Field Descriptions
      83. 8.6.83  RXPAT23 Register 0x04BE – Receive Pattern Register #23
        1. Table 106. RXPAT23 Field Descriptions
      84. 8.6.84  RXPAT24 Register 0x04BF – Receive Pattern Register #24
        1. Table 107. RXPAT24 Field Descriptions
      85. 8.6.85  RXPAT25 Register 0x04C0 – Receive Pattern Register #25
        1. Table 108. RXPAT25 Field Descriptions
      86. 8.6.86  RXPAT26 Register 0x04C1 – Receive Pattern Register #26
        1. Table 109. RXPAT26 Field Descriptions
      87. 8.6.87  RXPAT27 Register 0x04C2 Receive Pattern Register #27
        1. Table 110. RXPAT27 Field Descriptions
      88. 8.6.88  RXPAT28 Register 0x04C3 – Receive Pattern Register #28
        1. Table 111. RXPAT28 Field Descriptions
      89. 8.6.89  RXPAT29 Register 0x04C4 – Receive Pattern Register #29
        1. Table 112. RXPAT29 Field Descriptions
      90. 8.6.90  RXPAT30 Register 0x04C5 – Receive Pattern Register #30
        1. Table 113. RXPAT30 Field Descriptions
      91. 8.6.91  RXPAT31 Register 0x04C6 – Receive Pattern Register #31
        1. Table 114. RXPAT31 Field Descriptions
      92. 8.6.92  RXPAT32 Register 0x04C7 – Receive Pattern Register #32
        1. Table 115. RXPAT32 Field Descriptions
      93. 8.6.93  RXPBM1 Register 0x04C8 – Receive Pattern Byte Mask Register #1
        1. Table 116. RXPBM1 Field Descriptions
      94. 8.6.94  RXPBM2 Register 0x04C9 – Receive Pattern Byte Mask Register #2
        1. Table 117. RXPBM2 Field Descriptions
      95. 8.6.95  RXPBM3 Register 0x04CA – Receive Pattern Byte Mask Register #3
        1. Table 118. RXPBM3 Field Descriptions
      96. 8.6.96  RXPBM4 Register 0x04CB – Receive Pattern Byte Mask Register #4
        1. Table 119. RXPBM4 Field Descriptions
      97. 8.6.97  RXPATC Register 0x04CC – Receive Pattern Control Register
        1. Table 120. RXPATC Field Descriptions
      98. 8.6.98  RXD3CLK Register 0x04E0 – RX_D3 Clock Control Register
        1. Table 121. RXD3CLK Field Descriptions
      99. 8.6.99  LPS_CFG Register 0x04E5 – LPS Configuration Register
        1. Table 122. LPS_CFG Register 0x04E5 – LPS Configuration Register
      100. 8.6.100 PMA_CTRL1 Register 0x0007 – MMD1 PMA Control Register #1
        1. Table 123. PMA_CTRL1 Field Descriptions
      101. 8.6.101 PMA_EXT1 Register 0x000B – MMD1 PMA Extended Ability Register #1
        1. Table 124. PMA_EXT1 Field Descriptions
      102. 8.6.102 PMA_EXT2 Register 0x0012 – MMD1 PMA Extended Ability Register #2
        1. Table 125. PMA_EXT2 Field Descriptions
      103. 8.6.103 PMA_CTRL2 Register 0x0834 – MMD1 PMA Control Register #2
        1. Table 126. PMA_CTRL2 Field Descriptions
      104. 8.6.104 TEST_CTRL Register 0x0836 – MMD1 100BASE-T1 PMA Test Control Register
        1. Table 127. TEST_CTRL Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Metal Pour
      4. 11.1.4 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.13.3 Reduced Gigabit Media Independent Interface

The DP83TC811R-Q1 also supports Reduced Gigabit Media Independent Interface (RGMII) as specified by RGMII version 2.0 with LVCMOS. RGMII is designed to reduce the number of pins required to connect MAC and PHY. To accomplish this goal, the control signals are multiplexed. Both rising and falling edges of the clock are used to sample the control signal pin on transmit and receive paths. Data is samples on just the rising edge of the clock. For 100-Mbps operation, RX_CLK and TX_CLK operate at 25 MHz.

The RGMII signals are summarized in Table 12:

Table 12. RGMII Signals

FUNCTION PINS
Data Signals TX_D[3:0]
RX_D[3:0]
Control Signals TX_CTRL
RX_CTRL
Clock Signals TX_CLK
RX_CLK
DP83TC811R-Q1 RGMII_connection_snls551.gifFigure 26. RGMII Connections

Table 13. RGMII Transmit Encoding

TX_CTRL
(POSITIVE EDGE) 		TX_CTRL
(NEGATIVE EDGE) 		TX_D[3:0] DESCRIPTION
0 0 0000 through 1111 Normal Inter-Frame
0 1 0000 through 1111 Reserved
1 0 0000 through 1111 Normal Data Transmission
1 1 0000 through 1111 Transmit Error Propagation

Table 14. RGMII Receive Encoding

RX_CTRL
(POSITIVE EDGE) 		RX_CTRL
(NEGATIVE EDGE) 		RX_D[3:0] DESCRIPTION
0 0 0000 through 1111 Normal Inter-Frame
0 1 0000 through 1101 Reserved
0 1 1110 False Carrier Indication
0 1 1111 Reserved
1 0 0000 through 1111 Normal Data Reception
1 1 0000 through 1111 Data Reception with Errors

During packet reception, RX_CLK may be stretched on either the positive or negative pulse to accommodate the transition from the internal free running clock to a recovered clock (data synchronous). Data may be duplicated on the falling edge of the clock because double data rate (DDR) is only required for 1-Gbps operation, which is not supported by the DP83TC811R-Q1.

The DP83TC811R-Q1 supports in-band status indication to help simplify link status detection. Inter-frame signals on RX_D[3:0] pins as specified in Table 15.

Table 15. RGMII In-Band Status

RX_CTRL RX_D3 RX_D[2:1] RX_D0
00

Note:

In-band status is only valid when RX_CTRL is low		 Duplex Status:

0 = Half-Duplex

1 = Full-Duplex

 RX_CLK Clock Speed:

00 = 2.5 MHz

01 = 25 MHz

10 = 125 MHz

11 = Reserved

 Link Status:

0 = Link not established

1 = Valid link established