JAJSK47D August 2020 – December 2023 DP83TD510E
PRODUCTION DATA
Table 6-16 lists the DP83TD510E registers. All register offset addresses not listed in Table 6-16 should be considered as reserved locations and the register contents should not be modified.
DP83TD51010BaseT1L
Address | Acronym | Register Name | Section |
---|---|---|---|
0x0 | MII_REG_0 | Go | |
0x2 | MII_REG_2 | Go | |
0x3 | MII_REG_3 | Go | |
0x10 | PHY_STS | Go | |
0x11 | GEN_CFG | Go | |
0x12 | INTERRUPT_REG_1 | Go | |
0x13 | INTERRUPT_REG_2 | Go | |
0x15 | RX_ERR_CNT | Go | |
0x16 | BISCR | Go | |
0x17 | MAC_CFG_1 | Go | |
0x18 | MAC_CFG_2 | Go | |
0x19 | SOR_PHYAD | Go | |
0x1E | TDR_CFG | Go | |
0x119 | PRBS_CFG_1 | Go | |
0x11A | PRBS_CFG_2 | Go | |
0x11B | PRBS_CFG_3 | Go | |
0x11C | PRBS_STATUS_1 | Go | |
0x11D | PRBS_STATUS_2 | Go | |
0x11E | PRBS_STATUS_3 | Go | |
0x11F | PRBS_STATUS_4 | Go | |
0x120 | PRBS_STATUS_5 | Go | |
0x121 | PRBS_STATUS_6 | Go | |
0x122 | PRBS_STATUS_7 | Go | |
0x123 | PRBS_CFG_4 | Go | |
0x124 | PRBS_CFG_5 | Go | |
0x125 | PRBS_CFG_6 | Go | |
0x126 | PRBS_CFG_7 | Go | |
0x127 | PRBS_CFG_8 | Go | |
0x128 | PRBS_CFG_9 | Go | |
0x129 | PRBS_CFG_10 | Go | |
0x12A | CRC_STATUS | Go | |
0x12B | PKT_STAT_1 | Go | |
0x12C | PKT_STAT_2 | Go | |
0x12D | PKT_STAT_3 | Go | |
0x12E | PKT_STAT_4 | Go | |
0x12F | PKT_STAT_5 | Go | |
0x130 | PKT_STAT_6 | Go | |
0x200 | AN_CONTROL | Go | |
0x201 | AN_STATUS | Go | |
0x202 | AN_ADV_1 | Go | |
0x203 | AN_ADV_2 | Go | |
0x204 | AN_ADV_3 | Go | |
0x205 | AN_LP_ADV_1 | Go | |
0x206 | AN_LP_ADV_2 | Go | |
0x207 | AN_LP_ADV_3 | Go | |
0x208 | AN_NP_ADV_1 | Go | |
0x209 | AN_NP_ADV_2 | Go | |
0x20A | AN_NP_ADV_3 | Go | |
0x20B | AN_LP_NP_ADV_1 | Go | |
0x20C | AN_LP_NP_ADV_2 | Go | |
0x20D | AN_LP_NP_ADV_3 | Go | |
0x20E | AN_CTRL_10BT1 | Go | |
0x20F | AN_STATUS_10BT1 | Go | |
0x300 | TDR_CFG1 | Go | |
0x301 | TDR_CFG2 | Go | |
0x302 | TDR_CFG3 | Go | |
0x303 | FAULT_CFG1 | Go | |
0x304 | FAULT_CFG2 | Go | |
0x305 | FAULT_STAT1 | Go | |
0x306 | FAULT_STAT2 | Go | |
0x307 | FAULT_STAT3 | Go | |
0x308 | FAULT_STAT4 | Go | |
0x309 | FAULT_STAT5 | Go | |
0x30A | FAULT_STAT6 | Go | |
0x420 | CHIP_SOR_0 | Go | |
0x460 | LEDS_CFG_1 | Go | |
0x461 | IO_MUX_CFG | Go | |
0x462 | IO_MUX_GPIO_CTRL_1 | Go | |
0x463 | IO_MUX_GPIO_CTRL_2 | Go | |
0x467 | CHIP_SOR_1 | Go | |
0x468 | CHIP_SOR_2 | Go | |
0x469 | LEDS_CFG_2 | Go | |
0x60C | AN_STAT_1 | Go | |
0x872 | dsp_reg_72 | Go | |
0x88D | dsp_reg_8d | Go | |
0x88E | dsp_reg_8e | Go | |
0x88F | dsp_reg_8f | Go | |
0x890 | dsp_reg_90 | Go | |
0x891 | dsp_reg_91 | Go | |
0x892 | dsp_reg_92 | Go | |
0x898 | dsp_reg_98 | Go | |
0x899 | dsp_reg_99 | Go | |
0x89A | dsp_reg_9a | Go | |
0x89B | dsp_reg_9b | Go | |
0x89C | dsp_reg_9c | Go | |
0x89D | dsp_reg_9d | Go | |
0x8E9 | dsp_reg_e9 | Go | |
0x8EA | dsp_reg_ea | Go | |
0x8EB | dsp_reg_eb | Go | |
0x8EC | dsp_reg_ec | Go | |
0x8ED | dsp_reg_ed | Go | |
0x8EE | dsp_reg_ee | Go | |
0xA9D | alcd_metric | Go | |
0xA9F | alcd_status | Go | |
0xE01 | SCAN_2 | Go | |
0x1000 | PAM_PMD_CTRL_1 | Go | |
0x1007 | PMA_PMD_CTRL_2 | Go | |
0x100B | PMA_PMD_EXTENDED_ABILITY_2 | Go | |
0x1012 | PMA_PMD_EXTENDED_ABILITY | Go | |
0x1834 | PMA_PMD_CTRL | Go | |
0x18F6 | PMA_CTRL | Go | |
0x18F7 | PMA_STATUS | Go | |
0x18F8 | TEST_MODE_CTRL | Go | |
0x3000 | PCS_CTRL | Go | |
0x38E6 | PCS_CTRL_2 | Go | |
0x38E7 | PCS_STATUS | Go |
Complex bit access types are encoded to fit into small table cells. Table 6-17 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
W0C | W
0C |
Write
0 to clear |
W0S | W
0S |
Write
0 to set |
WMC | W | Write |
WSC | W | Write |
Reset or Default Value | ||
- n | Value after reset or the default value |
MII_REG_0 is shown in Table 6-18.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | mii_reset | R/WSC | 0x0 | 1b = Digital in reset and all MII regs (0x0 - 0xF) as well as interrupt status are reset to default
0b = No reset |
14 | loopback | R/WMC | 0x0 | 1b = MII loopback
0b = No MII loopback |
13 | RESERVED | R | 0x0 | Reserved |
12 | RESERVED | R | 0x0 | Reserved |
11 | power_down | R/WMC | 0x0 | 1b = Power down via register or pin
0b = Normal mode |
10 | isolate | R/WMC | 0x0 | 1b = Isolate mode
0b = Normal mode |
9 | RESERVED | R | 0x0 | Reserved |
8 | RESERVED | R | 0x0 | Reserved |
7 | RESERVED | R | 0x0 | Reserved |
6 | RESERVED | R | 0x0 | Reserved |
5 | unidirectional_ability | R | 0x0 | Reserved |
4-0 | RESERVED | R | 0x0 |
MII_REG_2 is shown in Table 6-19.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | oui_21_16 | R | 0x2000 |
MII_REG_3 is shown in Table 6-20.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | oui_5_0 | R | 0x0 | |
9-5 | model_number | R | 0xC | Model number |
4-0 | revision_number | R | 0x1 | Device revision number |
PHY_STS is shown in Table 6-21.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0x0 | |
7 | mii_interrupt | R/W0C | 0x0 | 1b = Interrupt pin had been set
0b = Interrupts pin not set |
6-1 | RESERVED | R | 0x0 | |
0 | link_status | R | 0x0 | 1b = Link is up
0b = Link is down |
GEN_CFG is shown in Table 6-22.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0x0 | Reserved |
14 | RESERVED | R | 0x0 | Reserved |
13-12 | RESERVED | R | 0x0 | Reserved |
11 | channel_debug_mode | R/W | 0x0 | |
10 | debug_mode | R/W | 0x0 | To reduce simulation time |
9-7 | RESERVED | R | 0x0 | |
6-5 | tx_fifo_depth | R/W | 0x1 | Fifo depth for RMII Tx fifo
00b = 4 nibbles 01b = 5 nibbles 10b = 6 nibbles 11b = 8 nibbles |
4 | RESERVED | R | 0x0 | |
3 | int_polarity | R/W | 0x1 | 1b = Interrupt pin is active low
0b = Interrupt pin active high |
2 | force_interrupt | R/W | 0x0 | Force interrupt pin to be active |
1 | int_en | R/W | 0x1 | 1b = Enable interrupt
0b = Disable interrupt |
0 | int_oe | R/W | 0x0 | 1b = MDINT_PWDN is interrupt pin
0b = MDINT_PWDN is power down pin |
INTERRUPT_REG_1 is shown in Table 6-23.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | rhf_int | R | 0x0 | Rx error cnt half full int status
Note : Latch high until read |
14 | RESERVED | R | 0x0 | |
13 | link_int | R | 0x0 | Link status change interrupt status
Note : Latch high until clear |
12 | RESERVED | R | 0x0 | Reserved |
11 | esd_int | R | 0x0 | ESD interrupt status
Note : Latch high until clear |
10-8 | RESERVED | R | 0x0 | |
7 | rhf_int_en | R/W | 0x0 | 1b = Enable rx_err_cnt half full interrupt
0b = Disable rx_err_cnt half full interrupt |
6 | RESERVED | R | 0x0 | |
5 | link_int_en | R/W | 0x0 | 1b = Enable link status change interrupt
0b = Disable link status change interrupt |
4 | RESERVED | R | 0x0 | Reserved |
3 | esd_int_en | R/W | 0x0 | 1b = Enable ESD interrupt
0b = Dsiable ESD interrupt |
2-0 | RESERVED | R | 0x0 |
INTERRUPT_REG_2 is shown in Table 6-24.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0x0 | |
13 | page_int | R | 0x0 | Aneg page received interrupt status
Note : Latch high until clear |
12-10 | RESERVED | R | 0x0 | |
9 | pol_int | R | 0x0 | Polarity change interrupt status
Note : Latch high until clear |
8 | RESERVED | R | 0x0 | Reserved |
7-6 | RESERVED | R | 0x0 | |
5 | page_int_en | R/W | 0x0 | 1b = Enable aneg page received interrupt
0b = Disable aneg page received interrupt |
4-2 | RESERVED | R | 0x0 | |
1 | pol_int_en | R/W | 0x0 | 1b = Enable polarity change interrupt
0b = Disable polarity change interrupt |
0 | RESERVED | R/W | 0x0 | Reserved |
RX_ERR_CNT is shown in Table 6-25.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | rx_err_cnt | R | 0x0 | Counts number of RX_ERR, saturates on max value
Note : Clear on read |
BISCR is shown in Table 6-26.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R | 0x0 | |
8 | core_pwr_mode | R | 0x1 | 1b = Core is in normal power mode
0b = Core is in power down/sleep mode |
7 | RESERVED | R | 0x0 | |
6-0 | loopback_mode | R/W | 0x0 | 0000001b = Reserved
0000010b = PCS loopback (Tx PAM3 to Rx PAM3) 0000100b = Digital loopback 0001000b = Analog loopback 0010000b = Reverse loopback 0100000b = Transmit to MAC in reverse loopback 1000000b = Transmit to MDI in MAC loopback |
MAC_CFG_1 is shown in Table 6-27.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | cfg_rmii_dis_delayed_txd_en | R/W | 0x0 | Reserved |
14 | min_ipg_mode_en | R/W | 0x1 | |
13 | cfg_rmii_enh | R/W | 0x0 | |
12 | cfg_rgmii_rx_clk_shift_sel | R/W | 0x0 | 1b = RGMII RX clock and data are shifted
0b = RGMII RX clock and data are aligned |
11 | cfg_rgmii_tx_clk_shift_sel | R/W | 0x0 | 1b = RGMII TX clock and data are shifted
0b = RGMII TX clock and data are aligned |
10 | RESERVED | R | 0x0 | |
9 | cfg_rgmii_en | R/W | 0x0 | 1b = RGMII enable
0b = RGMII disable |
8 | cfg_rmii_clk_shift_en | R/W | 0x0 | Reserved |
7 | cfg_xi_50 | R/W | 0x0 | 1b = XI is 50MHz
0b = XI is 25MHz |
6 | cfg_rmii_slow_mode | R/W | 0x0 | Setting this bit changes to RMII Master 5MHz mode from RMII Master 50MHz mode |
5 | cfg_rmii_mode | R/W | 0x0 | 1b = RMII MAC
0b = MII MAC (0x17[9] should be disabled) |
4 | cfg_rmii_rev1_0 | R/W | 0x0 | 1b = RMII rev1.0 (CRS_DV will toggle at the end of a packet to indicate deassertion of CRS)
0b = RMII rev1.2 (CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet) |
3 | rmii_ovf_sts | R/W0C | 0x0 | RMII fifo overflow indication |
2 | rmii_unf_sts | R/W0C | 0x0 | RMII fifo underflow indication |
1-0 | cfg_rmii_elast_buf | R/W | 0x1 | RMII rx fifo
00b = 14 bit tolerance (upto 16800 byte packet) 01b = 2 bit tolerance (upto 2400 byte packet) 10b = 6 bit tolerance (upto 7200 byte packet) 11b = 10 bit tolerance (upto 12000 byte packet) |
MAC_CFG_2 is shown in Table 6-28.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11 | cfg_inv_rx_clk | R/W | 0x0 | |
10 | cfg_rmii_crs_dv_sel | R/W | 0x0 | 1b = CRS is sent out on CRS_DV/RXDV for RMII
0b = DV is sent out on CRS_DV/RXDV for RMII |
9 | rgmii_tx_af_empty_err | R | 0x0 | |
8 | rgmii_tx_af_full_err | R | 0x0 | |
7-6 | RESERVED | R | 0x0 | Reserved |
5 | inv_rgmii_rxd | R/W | 0x0 | Swap 3:0 to 0:3 |
4 | inv_rgmii_txd | R/W | 0x0 | Swap 3:0 to 0:3 |
3 | sup_tx_err_fd_rgmii | R/W | 0x0 | 1b = Supress tx_err in full duplex when tx_en not active (CEXT)
0b = Normal |
2-0 | cfg_rgmii_half_full_th | R/W | 0x3 | RGMII TX sync FIFO half full threshold.
Option to reduce latency for RGMII: If the MAC and PHY are fed by same clock source (no PPM) we can lower the threshold from 2 to 1. |
SOR_PHYAD is shown in Table 6-29.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R | 0x0 | |
4-0 | SOR_PHYADDR | R | 0x0 |
TDR_CFG is shown in Table 6-30.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | tdr_start | R/WMC | 0x0 | Start TDR procedure. Following additional register configuration are needed. 0x0301 = 0x2403 0x0303 = 0x043E 0x030E = 0x2520 Please refer to Cabl Diagnostics App Note for detailed procedure |
14 | RESERVED | R | 0x0 | Reserved |
13-2 | RESERVED | R | 0x0 | |
1 | tdr_done | R | 0x0 | TDR done indication (only valid once TDR is started) |
0 | tdr_fail | R | 0x0 | TDR fail indication |
PRBS_CFG_1 is shown in Table 6-31.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0x0 | |
12 | send_pkt | R/WMC | 0x0 | Enables generating MAC packet with fix/incremental data w CRC
(pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear) Cleared automatically when pkt_done is set |
11 | RESERVED | R | 0x0 | |
10-8 | cfg_prbs_chk_sel | R/W | 0x5 | 000 : Checker receives from RGMII TX
010 : Checker receives from RMII TX 011 : Checker receives from MII TX 101 : Checker receives from Cu RX |
7 | RESERVED | R | 0x0 | |
6-4 | cfg_prbs_gen_sel | R/W | 0x7 | 000 : PRBS transmits to RGMII RX
010 : PRBS transmits to RMII RX 011 : PRBS transmits to MII RX 101 : PRBS transmits to Cu TX |
3 | cfg_prbs_cnt_mode | R/W | 0x0 | 1 = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again
0 = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting. |
2 | cfg_prbs_chk_enable | R/W | 0x1 | Enable PRBS checker xbar (to receive data)
To be enabled for rx packet counters to work |
1 | cfg_pkt_gen_prbs | R/W | 0x0 | If set:
(1) When pkt_gen_en is set, PRBS packets are generated continuously (3) When pkt_gen_en is cleared, PRBS RX checker is still enabled If cleared: (1) When pkt_gen_en is set, non - PRBS packet is generated (3) When pkt_gen_en is cleared, PRBS RX checker is disabled as well |
0 | pkt_gen_en | R/W | 0x0 | 1 = Enable packet/PRBS generator
0 = Disable packet/PRBS generato |
PRBS_CFG_2 is shown in Table 6-32.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | cfg_pkt_len_prbs | R/W | 0x5DC | Length (in bytes) of PRBS packets . This excludes CRC, Destination and Source address. |
PRBS_CFG_3 is shown in Table 6-33.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0x0 | |
12 | cfg_prbs_fix_patt_en | R/W | 0x0 | |
11-8 | cfg_prbs_fix_patt | R/W | 0x0 | |
7-0 | cfg_ipg_len | R/W | 0x7D | Inter-packet gap (in bytes) between packets |
PRBS_STATUS_1 is shown in Table 6-34.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | prbs_byte_cnt | R | 0x0 | Holds number of total bytes that received by the PRBS checker.
Value in this register is locked when write is done to register 0x11F bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFF |
PRBS_STATUS_2 is shown in Table 6-35.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | prbs_pkt_cnt_15_0 | R | 0x0 | Bits [15:0] of number of total packets received by the PRBS checker
Value in this register is locked when write is done to register 0x11F bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_STATUS_3 is shown in Table 6-36.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | prbs_pkt_cnt_31_16 | R | 0x0 | Bits [31:16] of number of total packets received by the PRBS checker
Value in this register is locked when write is done to register 0x11F bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_STATUS_4 is shown in Table 6-37.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0x0 | |
13 | prbs_sync_loss | R/W0C | 0x0 | 1b = PRBS has locked
0b = PRBS did not unlock |
12 | pkt_done | R | 0x0 | Set when all MAC packets w CRC are transmitted |
11 | pkt_gen_busy | R | 0x0 | 1 = Packet generator is in process
0 = Packet generator is not in process |
10 | prbs_pkt_ov | R | 0x0 | If set, packet counter reached overflow
Overflow is cleared when PRBS counters are cleared - done by setting bit #1 of 0x11f |
9 | prbs_byte_ov | R | 0x0 | If set, bytes counter reached overflow
Overflow is cleared when PRBS counters are cleared - done by setting bit #1 of 0x11f |
8 | prbs_lock | R | 0x0 | 1 = PRBS checker is locked sync) on received byte stream
0 = PRBS checker is not locked |
7-0 | prbs_err_cnt | R | 0x0 | Holds number of errored bits received by the PRBS checker
Value in this register is locked when write is done to bit[0] or bit[1] When PRBS Count Mode set to zero, count stops on 0xFF Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters |
PRBS_STATUS_5 is shown in Table 6-38.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0x0 | |
7-0 | prbs_err_ov_cnt | R | 0x0 | Holds number of error counter overflow that received by the PRBS checker.
Value in this register is locked when write is done to register 0x11f bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS counters work in single mode, overflow counter is not active |
PRBS_STATUS_6 is shown in Table 6-39.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | pkt_err_cnt_15_0 | R | 0x0 | Bits [15:0] of number of total packets with error received by the PRBS checker
Value in this register is locked when write is done to register 0x11f bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_STATUS_7 is shown in Table 6-40.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | pkt_err_cnt_31_16 | R | 0x0 | Bits [31:16] of number of total packets with error received by the PRBS checker
Value in this register is locked when write is done to register 0x11f bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_CFG_4 is shown in Table 6-41.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | cfg_pkt_data | R/W | 0x0 | Fixed data to be sent in Fix data mode |
7-6 | cfg_pkt_mode | R/W | 0x0 | 2'b00 - Incremental
2'b01 - Fixed 2'b1x - PRBS |
5-3 | cfg_pattern_vld_bytes | R/W | 0x0 | Number of bytes of valid pattern in packet (Max - 6) |
2-0 | cfg_pkt_cnt | R/W | 0x0 | 000b = 1 packet
001b = 10 packets 010b = 100 packets 011b = 1000 packets 100b = 10000 packets 101b = 100000 packets 110b = 1000000 packets 111b = Continuous packets |
PRBS_CFG_5 is shown in Table 6-42.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | pattern_15_0 | R/W | 0x0 | Bits 15:0 of pattern |
PRBS_CFG_6 is shown in Table 6-43.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | pattern_31_16 | R/W | 0x0 | Bits 31:16 of pattern |
PRBS_CFG_7 is shown in Table 6-44.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | pattern_47_32 | R/W | 0x0 | Bits 47:32 of pattern |
PRBS_CFG_8 is shown in Table 6-45.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | pmatch_data_15_0 | R/W | 0x0 | Bits 15:0 of Perfect Match Data - used for DA (destination address) match |
PRBS_CFG_9 is shown in Table 6-46.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | pmatch_data_31_16 | R/W | 0x0 | Bits 31:16 of Perfect Match Data - used for DA (destination address) match |
PRBS_CFG_10 is shown in Table 6-47.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | pmatch_data_47_32 | R/W | 0x0 | Bits 47:32 of Perfect Match Data - used for DA (destination address) match |
CRC_STATUS is shown in Table 6-48.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-2 | RESERVED | R | 0x0 | |
1 | rx_bad_crc | R | 0x0 | CRC error indication in packet received on Cu RX |
0 | tx_bad_crc | R | 0x0 | CRC error indication in packet transmitted on Cu TX |
PKT_STAT_1 is shown in Table 6-49.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | tx_pkt_cnt_15_0 | 0x0 | Lower 16 bits of Tx packet counter
Note : Register is cleared when 0x12B, 0x12C, 0x12D are read in sequence |
PKT_STAT_2 is shown in Table 6-50.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | tx_pkt_cnt_31_16 | 0x0 | Upper 16 bits of Tx packet counter
Note : Register is cleared when 0x12B, 0x12C, 0x12D are read in sequence |
PKT_STAT_3 is shown in Table 6-51.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | tx_err_pkt_cnt | 0x0 | Tx packet w error (CRC error) counter
Note : Register is cleared when 0x12B, 0x12C, 0x12D are read in sequence |
PKT_STAT_4 is shown in Table 6-52.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | rx_pkt_cnt_15_0 | 0x0 | Lower 16 bits of Rx packet counter
Note : Register is cleared when 0x12E, 0x12F, 0x130 are read in sequence |
PKT_STAT_5 is shown in Table 6-53.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | rx_pkt_cnt_31_16 | 0x0 | Upper 16 bits of Rx packet counter
Note : Register is cleared when 0x12E, 0x12F, 0x130 are read in sequence |
PKT_STAT_6 is shown in Table 6-54.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | rx_err_pkt_cnt | 0x0 | Rx packet w error (CRC error) counter
Note : Register is cleared when 0x12E, 0x12F, 0x130 are read in sequence |
AN_CONTROL is shown in Table 6-55.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | mr_main_reset | R | 0x0 | 1 = AN reset
0 = AN normal operation Note : Bit is self clearing |
14-13 | RESERVED | R | 0x0 | |
12 | mr_an_enable | R/W | 0x1 | 1 = enable Auto-Negotiation process
0 = disable Auto-Negotiation process |
11-10 | RESERVED | R | 0x0 | |
9 | mr_restart_an | R/WSC | 0x0 | 1 = Restart Auto-Negotiation process
0 = Auto-Negotiation in process, disabled, or not supported |
8-0 | RESERVED | R | 0x0 |
AN_STATUS is shown in Table 6-56.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-7 | RESERVED | R | 0x0 | |
6 | mr_page_received | R/W0C | 0x0 | 1 = A page has been received
0 = A page has not been received |
5 | mr_an_complete | R | 0x0 | 1 = Auto-Negotiation process completed
0 = Auto-Negotiation process not completed |
4 | remote_fault | R/W0C | 0x0 | 1 = remote fault condition detected
0 = no remote fault condition detected |
3 | mr_an_ability | R | 0x1 | 1 = PHY is able to perform Auto-Negotiation
0 = PHY is not able to perform Auto- Negotiation |
2 | link_status | R/W0S | 0x0 | 1 = Link is up
0 = Link is down |
1-0 | RESERVED | R | 0x0 |
AN_ADV_1 is shown in Table 6-57.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | mr_bp_np_ability | R/W | 0x0 | |
14 | mr_bp_ack | R | 0x0 | Always 0 |
13 | mr_bp_remote_fault | R/W | 0x0 | |
12-5 | mr_bp_12_5 | R/W | 0x0 | Bit 12 - Force Master/Slave
Bit 11:10 - Pause Bit 9:5 - Echoes nonce |
4-0 | selector_field | R/W | 0x1 | 00001b = IEEE802.3 |
AN_ADV_2 is shown in Table 6-58.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | mr_bp_31_16 | R/W | 0x0 | Bit 20:16 - Transmitted nonce
Bit 31:21 - A10 to A0 |
AN_ADV_3 is shown in Table 6-59.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | mr_bp_47_32 | R/W | 0x0 | A26 to A11 |
AN_LP_ADV_1 is shown in Table 6-60.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | mr_lp_bp_15_0 | R | 0x0 | LP' base page 15:0 |
AN_LP_ADV_2 is shown in Table 6-61.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | mr_lp_bp_31_16 | R | 0x0 | LP's base page 31:16 |
AN_LP_ADV_3 is shown in Table 6-62.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | mr_lp_bp_47_32 | R | 0x0 | LP's base page 47:32 |
AN_NP_ADV_1 is shown in Table 6-63.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | mr_np_np_ability | R/W | 0x0 | |
14 | RESERVED | R | 0x0 | |
13 | mr_np_message_page | R/W | 0x0 | |
12 | mr_np_ack2 | R/W | 0x0 | |
11 | mr_np_toggle | R | 0x0 | |
10-0 | mr_np_msg_unform_code_field | R/W | 0x0 | Predefined message codes |
AN_NP_ADV_2 is shown in Table 6-64.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | mr_np_unform_code_field_1 | R/W | 0x0 |
AN_NP_ADV_3 is shown in Table 6-65.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | mr_np_unform_code_field_2 | R/W | 0x0 |
AN_LP_NP_ADV_1 is shown in Table 6-66.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | mr_lp_np_np_ability | R | 0x0 | |
14 | mr_lp_np_ack | R | 0x0 | |
13 | mr_lp_np_message_page | R | 0x0 | |
12 | mr_lp_np_ack2 | R | 0x0 | |
11 | mr_lp_np_toggle | R | 0x0 | |
10-0 | mr_lp_np_msg_unform_code_field | R | 0x0 | Predefined message codes |
AN_LP_NP_ADV_2 is shown in Table 6-67.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | mr_lp_np_unform_code_field_1 | R | 0x0 |
AN_LP_NP_ADV_3 is shown in Table 6-68.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | mr_lp_np_unform_code_field_2 | R | 0x0 |
AN_CTRL_10BT1 is shown in Table 6-69.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | mr_10bt1_L_capability | R/W | 0x1 | 1 = Advertise PHY as 10BASE-T1L capable
0 = Do not advertise PHY as 10BASE-T1L capable |
14 | mr_ability_10bt1_L_eee | R/W | 0x0 | 1 = Advertise that the 10BASE-T1L PHY has EEE ability
0 = Do not advertise that the 10BASE-T1L PHY has EEE ability (default) |
13 | mr_ability_10bt1_L_incr_tx_rx_lvl | R/W | 0x1 | 1 = Advertise that the 10BASE-T1L PHY has increased transmit/receive level ability
0 = Do not advertise that the 10BASE-T1L PHY has increased transmit/receive level ability (default) |
12 | mr_10bt1_L_incr_tx_rx_lvl_rqst | R/W | 0x0 | 1 = Request 10BASE-T1L increased transmit level
0 = Do not request 10BASE-T1L increased transmit level (default) |
11-8 | RESERVED | R | 0x0 | |
7 | RESERVED | R | 0x0 | Reserved |
6 | RESERVED | R | 0x0 | Reserved |
5-0 | RESERVED | R | 0x0 |
AN_STATUS_10BT1 is shown in Table 6-70.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | mr_lp_10bt1_L_capability | R | 0x0 | 1 = Link partner is advertising PHY as 10BASE-T1L capable
0 = Link partner is not advertising PHY as 10BASE-T1L capable |
14 | mr_lp_ability_10bt1_L_eee | R | 0x0 | 1 = Link partner is advertising that the 10BASE-T1L PHY has EEE ability
0 = Link partner is not advertising that the 10BASE-T1L PHY has EEE ability |
13 | mr_lp_ability_10bt1_L_incr_tx_rx_lvl | R | 0x0 | 1 = Link partner is advertising that the 10BASE-T1L PHY has increased transmit/ receive level ability
0 = Link partner is not advertising that the 10BASE-T1L PHY has increased transmit/ receive level ability |
12 | mr_lp_10bt1_L_incr_tx_rx_lvl_rqst | R | 0x0 | 1 = Link partner is requesting 10BASE-T1L link partner increased transmit level
0 = Link partner is not requesting 10BASET1L link partner increased transmit level |
11-8 | RESERVED | R | 0x0 | |
7 | RESERVED | R | 0x0 | Reserved |
6 | RESERVED | R | 0x0 | Reserved |
5-0 | RESERVED | R | 0x0 |
TDR_CFG1 is shown in Table 6-71.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0x0 | |
12 | cfg_tdr_tx_type | R/W | 0x0 | Transmit voltage level for TDR
0 = 1V 1 = 2.4V |
11-8 | cfg_forward_shadow_2 | R/W | 0x5 | Forward shadow for segment 2 |
7-4 | cfg_forward_shadow_1 | R/W | 0x4 | Forward shadow for segment 1 |
3-2 | cfg_post_silence_time | R/W | 0x1 | post TDR silence time |
1-0 | cfg_pre_silence_time | R/W | 0x1 | pre TDR silence time |
TDR_CFG2 is shown in Table 6-72.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0x0 | |
14-8 | cfg_end_tap_index_1 | R/W | 0x24 | End tap index for echo coeff sweep for segment 1 |
7 | RESERVED | R | 0x0 | |
6-0 | cfg_start_tap_index_1 | R/W | 0x4 | Start tap index for echo coeff sweep for segment 1 |
TDR_CFG3 is shown in Table 6-73.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | cfg_tdr_tx_duration | R/W | 0x3E80 | TDR transmit duration in usec |
FAULT_CFG1 is shown in Table 6-74.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0x0 | |
14-8 | cfg_tdr_flt_loc_offset_1 | R/W | 0x5 | Tap index offset of dyamic peak equation for segment 1 |
7-0 | cfg_tdr_flt_init_1 | R/W | 0x3E | Offset of dynamic peak equation for segment 1 |
FAULT_CFG2 is shown in Table 6-75.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0x0 | |
7-0 | cfg_tdr_flt_slope_1 | R/W | 0xA | Slope of dynamic peak equation (*16 value) for segment 1 |
FAULT_STAT1 is shown in Table 6-76.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0x0 | |
14-8 | peaks_loc_1 | R | 0x0 | Location of 1st peak |
7 | RESERVED | R | 0x0 | |
6-0 | peaks_loc_0 | R | 0x0 | Location of 1st peak |
FAULT_STAT2 is shown in Table 6-77.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0x0 | |
14-8 | peaks_loc_3 | R | 0x0 | Location of 1st peak |
7 | RESERVED | R | 0x0 | |
6-0 | peaks_loc_2 | R | 0x0 | Location of 1st peak |
FAULT_STAT3 is shown in Table 6-78.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | peaks_amp_0 | R | 0x0 | Amplitude of 1st peak |
7 | RESERVED | R | 0x0 | |
6-0 | peaks_loc_4 | R | 0x0 | Location of 1st peak |
FAULT_STAT4 is shown in Table 6-79.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | peaks_amp_2 | R | 0x0 | Amplitude of 1st peak |
7-0 | peaks_amp_1 | R | 0x0 | Amplitude of 1st peak |
FAULT_STAT5 is shown in Table 6-80.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | peaks_amp_4 | R | 0x0 | Amplitude of 1st peak |
7-0 | peaks_amp_3 | R | 0x0 | Amplitude of 1st peak |
FAULT_STAT6 is shown in Table 6-81.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R | 0x0 | |
4 | peaks_sign_4 | R | 0x0 | Sign of 1st peak |
3 | peaks_sign_3 | R | 0x0 | Sign of 1st peak |
2 | peaks_sign_2 | R | 0x0 | Sign of 1st peak |
1 | peaks_sign_1 | R | 0x0 | Sign of 1st peak |
0 | peaks_sign_0 | R | 0x0 | Sign of 1st peak |
CHIP_SOR_0 is shown in Table 6-82.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
6 | read_strap_term_sl | R | 0x0 | Strap Value for for strap on Pin #8 |
5-0 | RESERVED | R | 0x0 |
LEDS_CFG_1 is shown in Table 6-83.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0x0 | Reserved |
14 | leds_bypass_stretching | R/W | 0x0 | 0 - Noraml Operation
1 - Bypass LEDs stretching |
13-12 | leds_blink_rate | R/W | 0x0 | 00 = 20Hz (50mSec)
01 = 10Hz (100mSec) 10 = 5Hz (200mSec) 11 = 2Hz (500mSec) |
11-8 | led_2_option | R/W | 0x5 | Controlls LED_2 sources
(same as bits 3:0) |
7-4 | led_1_option | R/W | 0x4 | Controlls LED_1 sources
(same as bits 3:0) |
3-0 | led_0_option | R/W | 0x8 | Controlls LED_0 source:
0x0 - link OK 0x1 - TX/RX activity 0x2 - TX activity 0x3 - RX activity 0x4 - LR 0x5 - SR 0x6 - LED SPEED : High for 10Base-T 0x7 - Duplex mode 0x8 - link + blink on activity w stretch option 0x9 - blink on activity w stretch option 0xA - blink on tx activity w stretch option 0xB - blink on rx activity w stretch option 0xC - link_lost 0xD - PRBS error (toggles on error) 0xE - XMII TX/RX Error with stretch option |
IO_MUX_CFG is shown in Table 6-84.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | io_oe_n_value | R/W | 0x0 | when io_oe_n_force_ctrl='1'
the direction of all IOs except MDC, MDIO and RESET_N is controlled via this bit: 0 - output 1 - Input |
14 | io_oe_n_force_ctrl | R/W | 0x0 | Debug option - enables forcing the direction of all IOs, except MDC, MDIO and RESET_N.
If set, IOs direction is controlled via bit #15 |
13-12 | pupd_value | R/W | 0x0 | when pupd_force_cntl='1'
the value of the pull up/down is control via this register |
11 | pupd_force_cntl | R/W | 0x0 | when '1' : all the PADs pull up/down is forced via registers |
10-6 | RESERVED | R | 0x0 | Reserved |
5-4 | impedance_ctrl | R/W | 0x0 | MAC interface PAD impedance control
bit #0 of this field is the slew control bit. If set to '1', slew rates will be faster (default is 0) |
3-2 | mac_rx_impedance_ctrl | R/W | 0x1 | MAC interface PAD impedance control
bit #0 of this field is the slew control bit. If set to '1', slew rates will be faster (default is 0) |
1-0 | mac_tx_impedance_ctrl | R/W | 0x1 | MAC interface PAD impedance control
bit #0 of this field is the slew control bit. If set to '1', slew rates will be faster (default is 0) |
IO_MUX_GPIO_CTRL_1 is shown in Table 6-85.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | led_2_clk_div_2_en | R/W | 0x0 | If led_2_gpio is configured to led_2_clk_source,
Selects divide by 2 of clock at led_2_clk_source |
14-12 | led_2_clk_source | R/W | 0x0 | In case clk_out is MUXed to LED_2 IO, this field controls clk_out source:
0 - XI clock 1 - LD 30MHz clock (Free/recovered based Master/Slave) 2 - 30 MHz ADC clock (recovered) 3 - Free 60MHz clock 4 - 7.5MHz clock (Free/recovered based Master/Slave) 5 - 25MHz clock to PLL (XI or XI/2) 6 - 2.5MHz clock (Free/recovered based Master/Slave) |
11 | led_2_clk_inv_en | R/W | 0x0 | If led_2_gpio is configured to led_2_clk_source,
Selects inversion of clock at led_2_clk_source |
10-8 | led_2_gpio_ctrl | R/W | 0x0 | controls the output of LED_2 IO:
0 - LED_2 1 - Clock out 2 - Interrupt 3 - 1'b0 4 - Reserved 5 -Reserved 6 - constant '0' 7 - constant '1' |
7 | led_0_clk_div_2_en | R/W | 0x0 | If led_0_gpio is configured to led_0_clk_source,
Selects divide by 2 of clock at led_0_clk_source |
6-4 | led_0_clk_source | R/W | 0x0 | In case clk_out is MUXed to LED_0 IO, this field controls clk_out source:
0 - XI clock 1 - LD 30MHz clock (Free/recovered based Master/Slave) 2 - 30 MHz ADC clock (recovered) 3 - Free 60MHz clock 4 - 7.5MHz clock (Free/recovered based Master/Slave) 5 - 25MHz clock to PLL (XI or XI/2) 6 - 2.5MHz clock (Free/recovered based Master/Slave) |
3 | led_0_clk_inv_en | R/W | 0x0 | If led_0_gpio is configured to led_0_clk_source,
Selects inversion of clock at led_0_clk_source |
2-0 | led_0_gpio_ctrl | R/W | 0x0 | controls the output of LED_0 IO:
0 - LED_0 1 - Clock out 2 - Interrupt 3 - 1'b0 4 -Reserved 5 - Reserve 6 - constant '0' 7 - constant '1' |
IO_MUX_GPIO_CTRL_2 is shown in Table 6-86.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | gpio_clk_source | R/W | 0x0 | In case clk_out is MUXed to GPIO IO, this field controls clk_out source:
0 - XI clock 1 - LD 30MHz clock (Free/recovered based Master/Slave) 2 - 30 MHz ADC clock (recovered) 3 - Free 60MHz clock 4 - 7.5MHz clock (Free/recovered based Master/Slave) 5 - 25MHz clock to PLL (XI or XI/2) 6 - 2.5MHz clock (Free/recovered based Master/Slave) |
12-10 | gpio_ctrl | R/W | 0x0 | controls the output of GPIO IO:
0 - LED_1 1 - Clock out 2 - Interrupt 3 - 1'b0 4 - Reserved 5 - Reserved 6 - constant '0' 7 - constant '1' |
9 | cfg_tx_er_on_led2 | R/W | 0x0 | 1b = LED_2 is used as TX_ER pin for MII |
8 | clk_o_clk_div_2_en | R/W | 0x0 | If clk_out is configured to output clk_o_clk_source,
Selects divide by 2 of clock at clk_o_clk_source |
7-4 | clk_o_clk_source | R/W | 0x0 | In case clk_out is MUXed to CLK_O IO, this field controls clk_out source:
0 - XI clock 1 - LD 30MHz clock (Free/recovered based Master/Slave) 2 - 30 MHz ADC clock (recovered) 3 - Free 60MHz clock 4 - 7.5MHz clock (Free/recovered based Master/Slave) 5 - 25MHz clock to PLL (XI or XI/2) 6 - 2.5MHz clock (Free/recovered based Master/Slave) 8 - CLK25_50 (50 MHz in RMII, 25 MHz in others) 9 - RMII RX 50MHz clock 10 - RMII TX 50MHz clock 11 - MII RX clock 12 - RGMII RX align clock 13 - RGMII RX shift clock |
3 | clk_o_clk_inv_en | R/W | 0x0 | If clk_out is configured to output clk_o_clk_source,
Selects inversion of clock at clk_o_clk_source |
2-0 | clk_o_gpio_ctrl | R/W | 0x0 | controls the output of CLK_O IO:
0 - LED_1 1 - Clock out 2 - Interrupt 3 - 1'b0 4 - Reserved 5 - Reserved 6 - constant '0' 7 - constant '1' |
CHIP_SOR_1 is shown in Table 6-87.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | sor_15_0 | R | 0x0 | SOR vector, bits [15:0] :
SOR[0] - RX_D3 SOR[1] - RX_D2 SOR[2] - RX_D1 SOR[3] - RX_D0 SOR[4] - CLK_OUT/LED_1 SOR[5] - RX_CTRL SOR[6] - RX_ER SOR[7] - LED_2 SOR[8] - LED_0 SOR[9] - GPIO |
CHIP_SOR_2 is shown in Table 6-88.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0x0 | Reserved |
3-0 | sor_19_16 | R | 0x0 | Reserved |
LEDS_CFG_2 is shown in Table 6-89.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0x0 | Reserved |
10 | led_2_polarity | R/W | 0x0 | LED_2 polarity:
0 - Active low 1 - Active high |
9 | led_2_drv_val | R/W | 0x0 | If bit #8 is set, this is the value of LED_2 |
8 | led_2_drv_en | R/W | 0x0 | 0 - LED_2 is in normal operation mode
1 - Drive the value of LED_2 (driven value is bit 9) |
7 | RESERVED | R | 0x0 | Reserved |
6 | led_1_polarity | R/W | 0x0 | LED_1 polarity:
0 - Active low 1 - Active high |
5 | led_1_drv_val | R/W | 0x0 | If bit #4 is set, this is the value of LED_1 |
4 | led_1_drv_en | R/W | 0x0 | 0 - LED_1 is in normal operation mode
1 - Drive the value of LED_1 (driven value is bit #5) |
3 | RESERVED | R | 0x0 | Reserved |
2 | led_0_polarity | R/W | 0x0 | LED_0 polarity:
0 - Active low 1 - Active high |
1 | led_0_drv_val | R/W | 0x0 | If bit #1 is set, this is the value of LED_1 |
0 | led_0_drv_en | R/W | 0x0 | 0 - LED_0 is in normal operation mode
1 - Drive the value of LED_0 (driven value is bit #1) |
AN_STAT_1 is shown in Table 6-90.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | master_slave_resol_fail | R | 0x0 | 1b = Master SLave resolution failed
0b = Master Slave resolution successful |
14-12 | an_state | R | 0x0 | |
11 | RESERVED | R | 0x0 | |
10-8 | hd_state | R | 0x0 | |
7 | RESERVED | R | 0x0 | |
6-4 | rx_state | R | 0x0 | |
3-0 | an_tx_state | R | 0x0 |
dsp_reg_72 is shown in Table 6-91.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0x0 | |
9-0 | mse_sqi | R | 0x0 | SQI : Reciever Avg Mean Square Value |
dsp_reg_8d is shown in Table 6-92.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_2p4_metric_step1 | R/W | 0x14 | ALCD reference metric for 0m for 2p4V mode |
dsp_reg_8e is shown in Table 6-93.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_2p4_metric_step2 | R/W | 0x1D | ALCD reference metric for 200m for 2p4V mode |
dsp_reg_8f is shown in Table 6-94.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_2p4_metric_step3 | R/W | 0x24 | ALCD reference metric for 400m for 2p4V mode |
dsp_reg_90 is shown in Table 6-95.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_2p4_metric_step4 | R/W | 0x35 | ALCD reference metric for 600m for 2p4V mode |
dsp_reg_91 is shown in Table 6-96.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_2p4_metric_step5 | R/W | 0x43 | ALCD reference metric for 800m for 2p4V mode |
dsp_reg_92 is shown in Table 6-97.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_2p4_metric_step6 | R/W | 0x60 | ALCD reference metric for 1000m for 2p4V mode |
dsp_reg_98 is shown in Table 6-98.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_1p0_metric_step1 | R/W | 0x2E | ALCD reference metric for 0m for 1p0V mode |
dsp_reg_99 is shown in Table 6-99.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_1p0_metric_step2 | R/W | 0x41 | ALCD reference metric for 200m for 1p0V mode |
dsp_reg_9a is shown in Table 6-100.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_1p0_metric_step3 | R/W | 0x58 | ALCD reference metric for 400m for 1p0V mode |
dsp_reg_9b is shown in Table 6-101.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_1p0_metric_step4 | R/W | 0x89 | ALCD reference metric for 600m for 1p0V mode |
dsp_reg_9c is shown in Table 6-102.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_1p0_metric_step5 | R/W | 0xB2 | ALCD reference metric for 800m for 1p0V mode |
dsp_reg_9d is shown in Table 6-103.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11-0 | cfg_alcd_1p0_metric_step6 | R/W | 0x107 | ALCD reference metric for 1000m for 1p0V mode |
dsp_reg_e9 is shown in Table 6-104.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0x0 | |
7-0 | cfg_alcd_cable_0 | R/W | 0x0 |
dsp_reg_ea is shown in Table 6-105.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0x0 | |
7-0 | cfg_alcd_cable_1 | R/W | 0x19 |
dsp_reg_eb is shown in Table 6-106.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0x0 | |
7-0 | cfg_alcd_cable_2 | R/W | 0x2F |
dsp_reg_ec is shown in Table 6-107.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0x0 | |
7-0 | cfg_alcd_cable_3 | R/W | 0x51 |
dsp_reg_ed is shown in Table 6-108.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0x0 | |
7-0 | cfg_alcd_cable_4 | R/W | 0x64 |
dsp_reg_ee is shown in Table 6-109.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0x0 | |
7-0 | cfg_alcd_cable_5 | R/W | 0x7A |
alcd_metric is shown in Table 6-110.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | ALCD_Metric_Value | R | 0x0 | |
3-0 | RESERVED | R | 0x0 | Reserved |
alcd_status is shown in Table 6-111.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | ALCD_Complete | R | 0x0 | 0 : In progress 1 : Complete |
14-11 | RESERVED | R | 0x0 | Reserved |
10-0 | ALCD_Cable_Length | R | 0x0 | In meters |
SCAN_2 is shown in Table 6-112.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R | 0x0 | |
8-4 | scan_state_saf | R | 0x1 | |
3 | cfg_en_efuse_burn | R | 0x0 | Enable the switch in the power supply path for EFUSE module
Note : This bit written by programming 0x0303 in 0x0E00 |
2-0 | RESERVED | R | 0x0 |
PAM_PMD_CTRL_1 is shown in Table 6-113.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PMA_Reset | R | 0x0 | 1b = PMA/PMD reset
0b = Normal operation Note : Read write bit, self clearing Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. Please remove 0x1 from [15:12] while using the address. |
14-12 | RESERVED | R | 0x0 | |
11 | cfg_low_power | R | 0x0 | 1b = Low-power mode
0b = Normal operation Note : Read write bit Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
10-1 | RESERVED | R | 0x0 | |
0 | PMA_loopback | R | 0x0 | 1 = Enable loopback mode
0 = Disable loopback mode Note : Read write bit Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. Please remove 0x1 from [15:12] while using the address. |
PMA_PMD_CTRL_2 is shown in Table 6-114.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-6 | RESERVED | R | 0x0 | |
5-0 | cfg_pma_type_selection | R | 0x3D | 111101b = BASE-T1 type selection for device
Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. Please remove 0x1 from [15:12] while using the address. |
PMA_PMD_EXTENDED_ABILITY_2 is shown in Table 6-115.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11 | base_t1_extended_abilities | R | 0x1 | 1b = PMA/PMD has BASE-T1 extended abilities listed in register
1.18 0b = PMA/PMD does not have BASE-T1 extended abilities Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
10-0 | RESERVED | R | 0x0 |
PMA_PMD_EXTENDED_ABILITY is shown in Table 6-116.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0x0 | |
3 | RESERVED | R | 0x0 | Reserved |
2 | mr_10_base_t1l_ability | R | 0x1 | 1b = PMA/PMD is able to perform 10BASE-T1L
0b = PMA/PMD is not able to perform 10BASE-T1L Prefixed 0x1 in [15:12] of address to differentiate.Please remove 0x1 from [15:12] while using the address. |
1 | RESERVED | R | 0x0 | Reserved |
0 | RESERVED | R | 0x0 | Reserved |
PMA_PMD_CTRL is shown in Table 6-117.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0x0 | |
14 | cfg_master_slave_val | R/W | 0x1 | 1b = Configure PHY as MASTER
0b = Configure PHY as SLAVE Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
13-4 | RESERVED | R | 0x0 | |
3-0 | cfg_type_selection | R | 0x2 | 0000b = Reserved
0001b = Reserved 0010b = 10BASE-T1L 0011b = Reserved 01xxb = Reserved 1xxxb = Reserved Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
PMA_CTRL is shown in Table 6-118.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PMA_Reset | R | 0x0 | 1 = PMA reset
0 = Normal operation Note : Read write bit, self clearing Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
14 | cfg_transmit_disable | R | 0x0 | 1 = Transmit disable
0 = Normal operation Note : Read write bit Prefixed 0x1 in [15:12] of address to differentiate.Please remove 0x1 from [15:12] while using the address. |
13 | RESERVED | R | 0x0 | |
12 | cfg_incr_tx_lvl | R/W | 0x0 | 1 = Enable 2.4 Vpp operating mode
0 = Enable 1.0 Vpp operating mode Prefixed 0x1 in [15:12] of address to differentiate.Please remove 0x1 from [15:12] while using the address. |
11 | cfg_low_power | R | 0x0 | 1 = Low-power mode
0 = Normal operation Note : Read write bit Prefixed 0x1 in [15:12] of address to differentiate.Please remove 0x1 from [15:12] while using the address. |
10 | cfg_eee_enable | R/W | 0x0 | 1 = Enable EEE mode
0 = Disable EEE mode Prefixed 0x1 in [15:12] of address to differentiate.Please remove 0x1 from [15:12] while using the address. |
9-1 | RESERVED | R | 0x0 | |
0 | PMA_loopback | R | 0x0 | 1 = Enable loopback mode
0 = Disable loopback mode Note : Read write bit Prefixed 0x1 in [15:12] of address to differentiate.Please remove 0x1 from [15:12] while using the address. |
PMA_STATUS is shown in Table 6-119.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0x0 | |
13 | loopback_ability | R | 0x1 | 1 = PHY has loopback ability
0 = PHY has no loopback ability Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
12 | tx_lvl_incr_ability | R | 0x1 | 1 = PHY has 2.4 Vpp operating mode ability
0 = PHY does not have 2.4 Vpp operating mode ability Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
11 | low_power_ability | R | 0x0 | 1 = PMA has low-power ability
0 = PMA does not have low-power ability Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
10 | eee_ability | R | 0x0 | 1 = PHY has EEE ability
0 = PHY does not have EEE ability Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
9 | receive_fault_ability | R | 0x0 | 1 = PMA has the ability to detect a fault condition on the receive path
0 = PMA does not have the ability to detect a fault condition on the receive path Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
8-3 | RESERVED | R | 0x0 | |
2 | receive_polarity | R | 0x0 | 1 = Receive polarity is reversed
0 = Receive polarity is not reversed Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
1 | receive_fault | R/W0C | 0x0 | 1 = Fault condition detected
0 = Fault condition not detected Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
0 | receive_link_status | R/W0S | 0x0 | 1 = PMA receive link up
0 = PMA receive link down Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
TEST_MODE_CTRL is shown in Table 6-120.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | cfg_test_mode | R/W | 0x0 | 1xxb = Reserved
011b = Test mode 3 010b = Test mode 2 001b = Test mode 1 000b = Normal (non-test) operation Prefixed 0x1 in [15:12] of address to differentiate. Please remove 0x1 from [15:12] while using the address. |
12-0 | RESERVED | R | 0x0 |
PCS_CTRL is shown in Table 6-121.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PCS_Reset | R | 0x0 | 1 = PCS reset
0 = Normal operation Note - RW bit, self clear bit Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
14 | mmd3_loopback | R | 0x0 | 1 = Enable loopback mode
0 = Disable loopback mode Note - RW bit Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
13-0 | RESERVED | R | 0x0 |
PCS_CTRL_2 is shown in Table 6-122.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PCS_Reset | R | 0x0 | 1 = PCS reset
0 = Normal operation Note - RW bit, self clear bit Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
14 | mmd3_loopback | R | 0x0 | 1 = Enable loopback mode
0 = Disable loopback mode Note - RW bit Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
13-0 | RESERVED | R | 0x0 |
PCS_STATUS is shown in Table 6-123.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0x0 | |
11 | tx_lpi_received | R/W0C | 0x0 | 1 = Tx PCS has received LPI
0 = LPI not received Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
10 | rx_lpi_received | R/W0C | 0x0 | 1 = Rx PCS has received LPI
0 = LPI not received Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
9 | tx_lpi_indication | R | 0x0 | 1 = Tx PCS is currently receiving LPI
0 = PCS is not currently receiving LPI Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
8 | rx_lpi_indication | R | 0x0 | 1 = Rx PCS is currently receiving LPI
0 = PCS is not currently receiving LPI Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
7 | fault | R/W0C | 0x0 | 1 = Fault condition detected
0 = No fault condition detected Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
6-3 | RESERVED | R | 0x0 | |
2 | receive_link_status | R/W0S | 0x0 | 1 = PCS receive link up
0 = PCS receive link down Prefixed 0x3 in [15:12] of address to differentiate. Please remove 0x3 from [15:12] while using the address. |
1-0 | RESERVED | R | 0x0 |