JAJSK47D August   2020  – December 2023 DP83TD510E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Auto-Negotiation (Speed Selection)
      2. 6.3.2  Repeater Mode
      3. 6.3.3  Media Converter
      4. 6.3.4  Clock Output
      5. 6.3.5  Media Independent Interface (MII)
      6. 6.3.6  Reduced Media Independent Interface (RMII)
      7. 6.3.7  RMII Low Power 5-MHz Mode
      8. 6.3.8  RGMII Interface
      9. 6.3.9  Serial Management Interface
      10. 6.3.10 Extended Register Space Access
        1. 6.3.10.1 Read (No Post Increment) Operation
        2. 6.3.10.2 Read (Post Increment) Operation
        3. 6.3.10.3 Write (No Post Increment) Operation
        4. 6.3.10.4 Write (Post Increment) Operation
      11. 6.3.11 Loopback Modes
        1. 6.3.11.1 MII Loopback
        2. 6.3.11.2 PCS Loopback
        3. 6.3.11.3 Digital Loopback
        4. 6.3.11.4 Analog Loopback
        5. 6.3.11.5 Far-End (Reverse) Loopback
      12. 6.3.12 BIST Configurations
      13. 6.3.13 Cable Diagnostics
        1. 6.3.13.1 TDR
        2. 6.3.13.2 Fast Link Down Functionality
    4. 6.4 Device Functional Modes
      1. 6.4.1 Straps Configuration
        1. 6.4.1.1 Straps for PHY Address
    5. 6.5 Programming
    6. 6.6 MMD Register Address Map
    7. 6.7 DP83TD510E Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Termination Circuit
        1. 7.2.1.1 Termination Circuit for Intrinsic Safe Applications
        2. 7.2.1.2 Components Range for Power Coupling/Decoupling
        3. 7.2.1.3 Termination Circuit for Non-Intrinsic Safe Applications
        4. 7.2.1.4 CMC Specifications
      2. 7.2.2 Design Requirements
        1. 7.2.2.1 Clock Requirements
          1. 7.2.2.1.1 Oscillator
          2. 7.2.2.1.2 Crystal
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Signal Traces
        2. 7.4.1.2 Return Path
        3. 7.4.1.3 Metal Pour
        4. 7.4.1.4 PCB Layer Stacking
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4.1.1 Straps for PHY Address

Table 6-8 PHY Address Strap Table
PIN NAME STRAP NAME PIN # DEFAULT
GPIO1 Strap9 32 0 PHY_ADD0
MODE 0 0
MODE 1 1
RX_ERR Strap6 20 0 PHY_ADD1
MODE 0 0
MODE 1 1
RX_D0 Strap4 16 0 PHY_ADD2
MODE 0 0
MODE 1 1
RX_D3 Strap1 13 0 PHY_ADD3
MODE 0 0
MODE 1 1

PHY Address strap is 4 bit strap on pin 13, 16, 20 and 32. It shall be read as [3:2:1:0] respectively. Default PHY Address is 0000.
Table 6-9 Reach Selection Strap
PIN NAME STRAP NAME PIN # DEFAULT
LED_2 Strap7 28 0 0

This Strap defines the voltage level requested by PHY during auto negotiation. It is reflected in bit 12 of 0x20E. While using Force mode for Linkup, the strap controls the output voltage and reflects in bit 12 of 0x18F6

0 : 2.4V & 1-V p2p
1 1: 1-V p2p
Table 6-10 MAC Mode Strap Table
PIN NAME STRAP NAME PIN # DEFAULT Strap8 Strap 3
RX_D1 Strap3 15 0 0 0 MII (default)
0 1 RMII Master
LED_0 Strap8 29 0 1 0

RGMII
1 1 RMII Slave
Table 6-11 RMII MAC Mode Strap Table
PIN NAME STRAP NAME PIN # DEFAULT
RX_D2 Strap2 14 0 0 Pin 18 is configured as CRS_DV (Default, for Media Conversion Mode)
1 Pin 18 is configured as RX_DV (For RMII Repeater or Media Conversion Mode)
Table 6-12 Terminations Selection
PIN NAME STRAP NAME PIN # DEFAULT
GPIO2 Strap10 8 Mandatory PU/PD 0 Receiver with tapping at 50 Ω (Recommended)
1 Receiver tapping at < 40 Ω
Table 6-13 Clockout/LED_1
PIN NAME STRAP NAME PIN # DEFAULT
RX_DV/CRS_DV Strap5 18 0 0 Clockout 25 M( default)
1 LED1