JAJSFR7F June 2016 – May 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718
PRODUCTION DATA.
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NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
5 | tosu(TXD-TXC) | Output Setup time, transmit selected signals valid to rgmiin_txc high/low | RGMII0, Internal Delay Enabled, 1000 Mbps | 1.05 (2) | ns | |
RGMII0, Internal Delay Enabled, 10/100 Mbps | 1.2 | ns | ||||
RGMII1, Internal Delay Enabled, 1000 Mbps | 1.05(3) | ns | ||||
RGMII1, Internal Delay Enabled, 10/100 Mbps | 1.2 | ns | ||||
6 | toh(TXC-TXD) | Output Hold time, transmit selected signals valid after rgmiin_txc high/low | RGMII0, Internal Delay Enabled, 1000 Mbps | 1.05 (2) | ns | |
RGMII0, Internal Delay Enabled, 10/100 Mbps | 1.2 | ns | ||||
RGMII1, Internal Delay Enabled, 1000 Mbps | 1.05(3) | ns | ||||
RGMII1, Internal Delay Enabled, 10/100 Mbps | 1.2 | ns |
In Table 5-112 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.
SIGNALS | IOSET3 | IOSET4 | ||
---|---|---|---|---|
BALL | MUX | BALL | MUX | |
GMAC RGMII1 | ||||
rgmii1_txd3 | C11 | 3 | ||
rgmii1_txd2 | B12 | 3 | ||
rgmii1_txd1 | A12 | 3 | ||
rgmii1_txd0 | A13 | 3 | ||
rgmii1_rxd3 | B13 | 3 | ||
rgmii1_rxd2 | E13 | 3 | ||
rgmii1_rxd1 | C13 | 3 | ||
rgmii1_rxd0 | D13 | 3 | ||
rgmii1_rxctl | F11 | 3 | ||
rgmii1_txc | B11 | 3 | ||
rgmii1_txctl | D11 | 3 | ||
rgmii1_rxc | E11 | 3 | ||
GMAC RGMII0 | ||||
rgmii0_txd3 | P4 | 0 | ||
rgmii0_txd2 | P3 | 0 | ||
rgmii0_txd1 | R2 | 0 | ||
rgmii0_txd0 | R1 | 0 | ||
rgmii0_rxd3 | N1 | 0 | ||
rgmii0_rxd2 | P1 | 0 | ||
rgmii0_rxd1 | N3 | 0 | ||
rgmii0_rxd0 | N4 | 0 | ||
rgmii0_txc | T4 | 0 | ||
rgmii0_rxctl | P2 | 0 | ||
rgmii0_rxc | N2 | 0 | ||
rgmii0_txctl | T5 | 0 |
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for GMAC. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-113Manual Functions Mapping for GMAC RGMII0 for a definition of the Manual modes.
Table 5-113 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | GMAC_RGMII0_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 0 | |||
N2 | rgmii0_rxc | 413 | 0 | CFG_RGMII0_RXC_IN | rgmii0_rxc |
P2 | rgmii0_rxctl | 27 | 2296 | CFG_RGMII0_RXCTL_IN | rgmii0_rxctl |
N4 | rgmii0_rxd0 | 3 | 1721 | CFG_RGMII0_RXD0_IN | rgmii0_rxd0 |
N3 | rgmii0_rxd1 | 134 | 1786 | CFG_RGMII0_RXD1_IN | rgmii0_rxd1 |
P1 | rgmii0_rxd2 | 40 | 1966 | CFG_RGMII0_RXD2_IN | rgmii0_rxd2 |
N1 | rgmii0_rxd3 | 0 | 2057 | CFG_RGMII0_RXD3_IN | rgmii0_rxd3 |
T4 | rgmii0_txc | 0 | 60 | CFG_RGMII0_TXC_OUT | rgmii0_txc |
T5 | rgmii0_txctl | 0 | 60 | CFG_RGMII0_TXCTL_OUT | rgmii0_txctl |
R1 | rgmii0_txd0 | 0 | 60 | CFG_RGMII0_TXD0_OUT | rgmii0_txd0 |
R2 | rgmii0_txd1 | 0 | 0 | CFG_RGMII0_TXD1_OUT | rgmii0_txd1 |
P3 | rgmii0_txd2 | 0 | 60 | CFG_RGMII0_TXD2_OUT | rgmii0_txd2 |
P4 | rgmii0_txd3 | 0 | 120 | CFG_RGMII0_TXD3_OUT | rgmii0_txd3 |
Manual IO Timings Modes must be used to ensure some IO timings for GMAC. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-114Manual Functions Mapping for GMAC RGMII1 for a definition of the Manual modes.
Table 5-114 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | GMAC_RGMII1_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 3 | |||
E11 | vin2a_d18 | 530 | 0 | CFG_VIN2A_D18_IN | rgmii1_rxc |
F11 | vin2a_d19 | 71 | 1099 | CFG_VIN2A_D19_IN | rgmii1_rxctl |
B13 | vin2a_d20 | 142 | 1337 | CFG_VIN2A_D20_IN | rgmii1_rxd3 |
E13 | vin2a_d21 | 114 | 1517 | CFG_VIN2A_D21_IN | rgmii1_rxd2 |
C13 | vin2a_d22 | 171 | 1331 | CFG_VIN2A_D22_IN | rgmii1_rxd1 |
D13 | vin2a_d23 | 0 | 1328 | CFG_VIN2A_D23_IN | rgmii1_rxd0 |
B11 | vin2a_d12 | 0 | 0 | CFG_VIN2A_D12_OUT | rgmii1_txc |
D11 | vin2a_d13 | 170 | 0 | CFG_VIN2A_D13_OUT | rgmii1_txctl |
C11 | vin2a_d14 | 150 | 0 | CFG_VIN2A_D14_OUT | rgmii1_txd3 |
B12 | vin2a_d15 | 0 | 0 | CFG_VIN2A_D15_OUT | rgmii1_txd2 |
A12 | vin2a_d16 | 60 | 0 | CFG_VIN2A_D16_OUT | rgmii1_txd1 |
A13 | vin2a_d17 | 60 | 0 | CFG_VIN2A_D17_OUT | rgmii1_txd0 |