JAJSFR7 データシート

JAJSFR7F June 2016 – May 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718

PRODUCTION DATA.

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

CBD|538

サーマルパッド・メカニカル・データ

発注情報

jajsfr7f_oa

4.3.26.2 Power, Reset, and Clock Management (PRCM)

NOTE

For more information, see PRCM section of the device TRM.

Table 4-28 PRCM Signal Descriptions

SIGNAL NAME	DESCRIPTION	TYPE	BALL
clkout1	Device Clock output 1. Can be used externally for devices with non-critical timing requirements, or for debug, or as a reference clock on GPMC as described in Table 5-48GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 5-50GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate.	O	K23, L4
clkout2	Device Clock output 2. Can be used externally for devices with non-critical timing requirements, or for debug.	O	H5, J25
clkout3	Device Clock output 3. Can be used xternally for devices with non-critical timing requirements, or for debug.	O	H25
porz	Power on Reset (active low) input must be asserted low during a device power up sequence or cold reset state when all supplies are disabled. Typically, an external PMIC is the source and sets porz high after all supplies reach valid operating levels. Asserting porz low puts the entire device in a safe reset state.	I	F19
resetn	Reset (active low) input’s falling edge can trigger a device warm reset state from an external component. This signal should be high prior to or simultaneous with, porz rising. If the signal is not used in the system, resetn should be pulled high with an external pull-up resistor to vddshv3.	I	K24
rstoutn	Reset out (Active low) output is asserted low whenever any global reset condition exists. After a brief delay, it will be set high upon removal of the internal global reset condition (i.e. porz, warm reset). It is only functional after its output buffer’s reference voltage (vddshv3) is valid. If it is used as a reset for device peripheral components, then it should be AND gated with porz to avoid the possibility of reset signal glitches during a power up sequence.^⁽²⁾	O	E20
xi_osc0	System Oscillator OSC0 Crystal input / LVCMOS clock input. Functions as the input connection to a crystal when the internal oscillator OSC0 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used.	I	Y12
xi_osc1	Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input. Functions as the input connection to a crystal when the internal oscillator OSC1 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used	I	AC11
xo_osc0	System Oscillator OSC0 Crystal output	O	AB12
xo_osc1	Auxiliary Oscillator OSC1 Crystal output	O	AA11
xref_clk0	External Reference Clock 0. For Audio and other Peripherals.	I	J25
xref_clk1	External Reference Clock 1. For Audio and other Peripherals.	I	J24
xref_clk2	External Reference Clock 2. For Audio and other Peripherals.	I	H24
xref_clk3	External Reference Clock 3. For Audio and other Peripherals.	I	H25
RMII_MHZ_50_CLK^⁽¹⁾	RMII Reference Clock (50MHz). This pin is an input when external reference is used or output when internal reference is used.	IO	P5

This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V_IH and V_IL must be less than V_HYS.
Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.