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DATA SHEET
DRA75xP, DRA74xP Infotainment Applications Processor Silicon Revision 1.0
1 Device Overview
1.1 Features
- Architecture Designed for Infotainment Applications
- Video, Image, and Graphics Processing Support
- Full-HD Video (1920 × 1080p, 60 fps)
- Multiple Video Input and Video Output
- 2D and 3D Graphics
- Dual Arm®Cortex®-A15 Microprocessor Subsystem
- Up to Two C66x Floating-Point VLIW DSP
- Fully Object-Code Compatible with C67x and C64x+
- Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
- Up to 2.5MB of On-Chip L3 RAM
- Level 3 (L3) and Level 4 (L4) Interconnects
- Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
- Supports up to DDR2-800 and DDR3-1333
- Up to 2GB Supported per EMIF
- Dual ARM® Cortex®-M4 Image Processing Units (IPU)
- Up to Two Embedded Vision Engines (EVEs)
- Imaging Subsystem (ISS)
- Image Signal Processor (ISP)
- Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
- One Camera Adaptation Layer (CAL_B)
- IVA Subsystem
- Display Subsystem
- Display Controller with DMA Engine and up to Three Pipelines
- HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
- Video Processing Engine (VPE)
- 2D-Graphics Accelerator (BB2D) Subsystem
- Dual-Core PowerVR® SGX544 3D GPU
- Two Video Input Port (VIP) Modules
- Support for up to Eight Multiplexed Input Ports
- General-Purpose Memory Controller (GPMC)
- Enhanced Direct Memory Access (EDMA) Controller
- 2-Port Gigabit Ethernet (GMAC)
- Sixteen 32-Bit General-Purpose Timers
- 32-Bit MPU Watchdog Timer
- Five Inter-Integrated Circuit (I2C) Ports
- HDQ™/1-Wire® Interface
- SATA Interface
- Media Local Bus (MLB) Subsystem
- Ten Configurable UART/IrDA/CIR Modules
- Four Multichannel Serial Peripheral Interfaces (McSPI)
- Quad SPI (QSPI)
- Eight Multichannel Audio Serial Port (McASP) Modules
- SuperSpeed USB 3.0 Dual-Role Device
- Three High-Speed USB 2.0 Dual-Role Devices
- Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
- PCI Express® 3.0 Subsystems with Two 5-Gbps Lanes
- One 2-Lane Gen2-Compliant Port
- or Two 1-Lane Gen2-Compliant Ports
- Up to Two Controller Area Network (DCAN) Modules
- Modular Controller Area Network (MCAN) Module
- CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
- Up to 247 General-Purpose I/O (GPIO) Pins
- Real-Time Clock Subsystem (RTCSS)
- Device Security Features
- Hardware Crypto Accelerators and DMA
- Firewalls
- JTAG® Lock
- Secure Keys
- Secure ROM and Boot
- Customer Programmable Keys and OTP Data
- Power, Reset, and Clock Management
- On-Chip Debug with CTools Technology
- 28-nm CMOS Technology
- 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)
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