JAJSGK8F December   2015  – May 2019 DRA745 , DRA746 , DRA750 , DRA756

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2 改訂履歴
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  External Memory Interface (EMIF)
      5. 4.4.5  General-Purpose Memory Controller (GPMC)
      6. 4.4.6  Timers
      7. 4.4.7  Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8  HDQ / 1-Wire Interface (HDQ1W)
      9. 4.4.9  Universal Asynchronous Receiver Transmitter (UART)
      10. 4.4.10 Multichannel Serial Peripheral Interface (McSPI)
      11. 4.4.11 Quad Serial Peripheral Interface (QSPI)
      12. 4.4.12 Multichannel Audio Serial Port (McASP)
      13. 4.4.13 Universal Serial Bus (USB)
      14. 4.4.14 SATA
      15. 4.4.15 Peripheral Component Interconnect Express (PCIe)
      16. 4.4.16 Controller Area Network Interface (DCAN)
      17. 4.4.17 Ethernet Interface (GMAC_SW)
      18. 4.4.18 Media Local Bus (MLB) Interface
      19. 4.4.19 eMMC/SD/SDIO
      20. 4.4.20 General-Purpose Interface (GPIO)
      21. 4.4.21 Keyboard controller (KBD)
      22. 4.4.22 Pulse Width Modulation (PWM) Interface
      23. 4.4.23 Audio Tracking Logic (ATL)
      24. 4.4.24 Test Interfaces
      25. 4.4.25 System and Miscellaneous
        1. 4.4.25.1 Sysboot
        2. 4.4.25.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.25.3 Real Time Clock (RTC) Interface
        4. 4.4.25.4 System Direct Memory Access (SDMA)
        5. 4.4.25.5 Interrupt Controllers (INTC)
        6. 4.4.25.6 Observability
      26. 4.4.26 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  ILVDS18 Buffers DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 PCIEPHY DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 RC On-die Oscillator Clock
    3. 6.3 DPLLs, DLLs Specifications
      1. 6.3.1 DPLL Characteristics
      2. 6.3.2 DLL Characteristics
      3. 6.3.3 DPLL and DLL Noise Isolation
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem – Video Output Ports
    8. 7.8  Display Subsystem – High-Definition Multimedia Interface (HDMI)
    9. 7.9  External Memory Interface (EMIF)
    10. 7.10 General-Purpose Memory Controller (GPMC)
      1. 7.10.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11 Timers
    12. 7.12 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-34 Timing Requirements for I2C Input Timings
      2. Table 7-35 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-36 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    13. 7.13 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.13.1 HDQ / 1-Wire — HDQ Mode
      2. 7.13.2 HDQ/1-Wire—1-Wire Mode
    14. 7.14 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-41 Timing Requirements for UART
      2. Table 7-42 Switching Characteristics Over Recommended Operating Conditions for UART
    15. 7.15 Multichannel Serial Peripheral Interface (McSPI)
    16. 7.16 Quad Serial Peripheral Interface (QSPI)
    17. 7.17 Multichannel Audio Serial Port (McASP)
      1. Table 7-49 Timing Requirements for McASP1
      2. Table 7-50 Timing Requirements for McASP2
      3. Table 7-51 Timing Requirements for McASP3/4/5/6/7/8
      4. Table 7-52 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-53 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-54 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
    18. 7.18 Universal Serial Bus (USB)
      1. 7.18.1 USB1 DRD PHY
      2. 7.18.2 USB2 PHY
      3. 7.18.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
    19. 7.19 Serial Advanced Technology Attachment (SATA)
    20. 7.20 Peripheral Component Interconnect Express (PCIe)
    21. 7.21 Controller Area Network Interface (DCAN)
      1. Table 7-69 Timing Requirements for DCANx Receive
      2. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    22. 7.22 Ethernet Interface (GMAC_SW)
      1. 7.22.1 GMAC MII Timings
        1. Table 7-71 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-72 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-73 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-74 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.22.2 GMAC MDIO Interface Timings
      3. 7.22.3 GMAC RMII Timings
        1. Table 7-79 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-80 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-81 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-82 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.22.4 GMAC RGMII Timings
        1. Table 7-86 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-87 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-88 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-89 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    23. 7.23 Media Local Bus (MLB) interface
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1—SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 — eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.24.3 MMC3 and MMC4—SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 Audio Tracking Logic (ATL)
      1. 7.26.1 ATL Electrical Data/Timing
        1. Table 7-145 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
          1. Table 7-146 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-147 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-148 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-149 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Introduction
      1. 8.1.1 Initial Requirements and Guidelines
    2. 8.2 Power Optimizations
      1. 8.2.1 Step 1: PCB Stack-up
      2. 8.2.2 Step 2: Physical Placement
      3. 8.2.3 Step 3: Static Analysis
        1. 8.2.3.1 PDN Resistance and IR Drop
      4. 8.2.4 Step 4: Frequency Analysis
      5. 8.2.5 System ESD Generic Guidelines
        1. 8.2.5.1 System ESD Generic PCB Guideline
        2. 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 8.2.6 EMI / EMC Issues Prevention
        1. 8.2.6.1 Signal Bandwidth
        2. 8.2.6.2 Signal Routing
          1. 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 8.2.6.3 Ground Guidelines
          1. 8.2.6.3.1 PCB Outer Layers
          2. 8.2.6.3.2 Metallic Frames
          3. 8.2.6.3.3 Connectors
          4. 8.2.6.3.4 Guard Ring on PCB Edges
          5. 8.2.6.3.5 Analog and Digital Ground
    3. 8.3 Core Power Domains
      1. 8.3.1 General Constraints and Theory
      2. 8.3.2 Voltage Decoupling
      3. 8.3.3 Static PDN Analysis
      4. 8.3.4 Dynamic PDN Analysis
      5. 8.3.5 Power Supply Mapping
      6. 8.3.6 DPLL Voltage Requirement
      7. 8.3.7 Loss of Input Power Event
      8. 8.3.8 Example PCB Design
        1. 8.3.8.1 Example Stack-up
        2. 8.3.8.2 vdd_mpu Example Analysis
    4. 8.4 Single-Ended Interfaces
      1. 8.4.1 General Routing Guidelines
      2. 8.4.2 QSPI Board Design and Layout Guidelines
    5. 8.5 Differential Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1 Background
        2. 8.5.2.2 USB PHY Layout Guide
          1. 8.5.2.2.1 General Routing and Placement
          2. 8.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3  Board Stackup
            4. 8.5.2.2.2.4  Cable Connector Socket
            5. 8.5.2.2.2.5  Clock Routings
            6. 8.5.2.2.2.6  Crystals/Oscillator
            7. 8.5.2.2.2.7  DP/DM Trace
            8. 8.5.2.2.2.8  DP/DM Vias
            9. 8.5.2.2.2.9  Image Planes
            10. 8.5.2.2.2.10 JTAG Interface
            11. 8.5.2.2.2.11 Power Regulators
        3. 8.5.2.3 Electrostatic Discharge (ESD)
          1. 8.5.2.3.1 IEC ESD Stressing Test
            1. 8.5.2.3.1.1 Test Mode
            2. 8.5.2.3.1.2 Air Discharge Mode
            3. 8.5.2.3.1.3 Test Type
          2. 8.5.2.3.2 TI Component Level IEC ESD Test
          3. 8.5.2.3.3 Construction of a Custom USB Connector
          4. 8.5.2.3.4 ESD Protection System Design Consideration
        4. 8.5.2.4 References
      3. 8.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1 USB 3.0 interface introduction
        2. 8.5.3.2 USB 3.0 General routing rules
      4. 8.5.4 HDMI Board Design and Layout Guidelines
        1. 8.5.4.1 HDMI Interface Schematic
        2. 8.5.4.2 TMDS General Routing Guidelines
        3. 8.5.4.3 TPD5S115
        4. 8.5.4.4 HDMI ESD Protection Device (Required)
        5. 8.5.4.5 PCB Stackup Specifications
        6. 8.5.4.6 Grounding
      5. 8.5.5 SATA Board Design and Layout Guidelines
        1. 8.5.5.1 SATA Interface Schematic
        2. 8.5.5.2 Compatible SATA Components and Modes
        3. 8.5.5.3 PCB Stackup Specifications
        4. 8.5.5.4 Routing Specifications
      6. 8.5.6 PCIe Board Design and Layout Guidelines
        1. 8.5.6.1 PCIe Connections and Interface Compliance
          1. 8.5.6.1.1 Coupling Capacitors
          2. 8.5.6.1.2 Polarity Inversion
        2. 8.5.6.2 Non-standard PCIe connections
          1. 8.5.6.2.1 PCB Stackup Specifications
          2. 8.5.6.2.2 Routing Specifications
            1. 8.5.6.2.2.1 Impedance
            2. 8.5.6.2.2.2 Differential Coupling
            3. 8.5.6.2.2.3 Pair Length Matching
        3. 8.5.6.3 LJCB_REFN/P Connections
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
    7. 8.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 8.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 8.7.2 DDR2 Board Design and Layout Guidelines
        1. 8.7.2.1 Board Designs
        2. 8.7.2.2 DDR2 Interface
          1. 8.7.2.2.1  DDR2 Interface Schematic
          2. 8.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 8.7.2.2.3  PCB Stackup
          4. 8.7.2.2.4  Placement
          5. 8.7.2.2.5  DDR2 Keepout Region
          6. 8.7.2.2.6  Bulk Bypass Capacitors
          7. 8.7.2.2.7  High-Speed Bypass Capacitors
          8. 8.7.2.2.8  Net Classes
          9. 8.7.2.2.9  DDR2 Signal Termination
          10. 8.7.2.2.10 VREF Routing
        3. 8.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 8.7.3 DDR3 Board Design and Layout Guidelines
        1. 8.7.3.1  Board Designs
          1. 8.7.3.1.1 DDR3 versus DDR2
        2. 8.7.3.2  DDR3 EMIFs
        3. 8.7.3.3  DDR3 Device Combinations
        4. 8.7.3.4  DDR3 Interface Schematic
          1. 8.7.3.4.1 32-Bit DDR3 Interface
          2. 8.7.3.4.2 16-Bit DDR3 Interface
        5. 8.7.3.5  Compatible JEDEC DDR3 Devices
        6. 8.7.3.6  PCB Stackup
        7. 8.7.3.7  Placement
        8. 8.7.3.8  DDR3 Keepout Region
        9. 8.7.3.9  Bulk Bypass Capacitors
        10. 8.7.3.10 High-Speed Bypass Capacitors
          1. 8.7.3.10.1 Return Current Bypass Capacitors
        11. 8.7.3.11 Net Classes
        12. 8.7.3.12 DDR3 Signal Termination
        13. 8.7.3.13 VREF_DDR Routing
        14. 8.7.3.14 VTT
        15. 8.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.3.15.1 Four DDR3 Devices
            1. 8.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.3.15.2 Two DDR3 Devices
            1. 8.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.3.15.3 One DDR3 Device
            1. 8.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.3.16 Data Topologies and Routing Definition
          1. 8.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.3.17 Routing Specification
          1. 8.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.7.3.17.2 DQS and DQ Routing Specification
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 商標
    7. 9.7 静電気放電に関する注意事項
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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発注情報

7.7 Display Subsystem – Video Output Ports

Three Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1, DPI Video Output 2 and DPI Video Output 3.

NOTE

The DPI Video Output i (i = 1 to 3) interface is also referred to as VOUTi.

Every VOUT interface consists of:

  • 24-bit data bus (data[23:0])
  • Horizontal synchronization signal (HSYNC)
  • Vertical synchronization signal (VSYNC)
  • Data enable (DE)
  • Field ID (FID)
  • Pixel clock (CLK)

NOTE

For more information, see the Display Subsystem chapter of the Device TRM.

CAUTION

The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in the Table 7-19 and Table 7-20.

CAUTION

The IO Timings provided in this section are only valid for some DSS usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section.

CAUTION

All pads/balls configured as vouti_* signals are recommended to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1). FAST slew setting is allowed, but results in faster edge rates on the VOUTn bus, higher power/ground noise, and higher EMI emissions compared to SLOW slew rate.

Table 7-15, Table 7-16 and Figure 7-6 assume testing over the recommended operating conditions and electrical characteristic conditions.

Table 7-15 DPI Video Output i (i = 1..3) Default Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk 11.76 (2) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low DPI1, DPI2 (IOSET1), DPI3 P*0.5-1 (1) ns
DPI2 (IOSET2) P*0.5-1.35 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high DPI1, DPI2 (IOSET1), DPI3 P*0.5-1 (1) ns
DPI2 (IOSET2) P*0.5-1.35 (1) ns
D5 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI1 -2.5 2.5 ns
DPI2 (IOSET1) -2.5 2.5 ns
DPI2 (IOSET2) -2.5 2.5 ns
DPI3 (IOSET1) -2.5 2.5 ns
DPI3 (IOSET2/3) -2.5 2.5 ns
D6 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI1 -2.5 2.5 ns
DPI2 (IOSET1) -2.5 2.5 ns
DPI2 (IOSET2) -2.5 2.5 ns
DPI3 (IOSET1) -2.5 2.5 ns
DPI3 (IOSET2/3) -2.5 2.5 ns
  1. P = output vouti_clk period in ns.
  2. All pads/balls configured as vouti_* signals are recommended to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1). FAST slew setting is allowed, but results in faster edge rates on the VOUTn bus, higher power/ground noise, and higher EMI emissions compared to SLOW slew rate.
  3. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.

Table 7-16 DPI Video Output i (i = 1..3) Alternate Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk 6.06 (2) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI1 1.51 4.55 ns
DPI2 (IOSET1) 1.51 4.55 ns
DPI2 (IOSET2) 1.51 4.55 ns
DPI3 1.51 4.55 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI1 1.51 4.55 ns
DPI2 (IOSET1) 1.51 4.55 ns
DPI2 (IOSET2) 1.51 4.55 ns
DPI3 1.51 4.55 ns
  1. P = output vouti_clk period in ns.
  2. All pads/balls configured as vouti_* signals are recommended to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1). FAST slew setting is allowed, but results in faster edge rates on the VOUTn bus, higher power/ground noise, and higher EMI emissions compared to SLOW slew rate.
  3. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.

Table 7-17 DPI Video Output i (i = 1..3) MANUAL3 Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk 6.06 (2) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI1 2.85 5.56 ns
DPI2, DPI3 2.78 5.91 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI1 2.85 5.56 ns
DPI2, DPI3 2.78 5.91 ns
  1. P = output vouti_clk period in ns.
  2. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.

Table 7-18 DPI Video Output i (i = 1..3) MANUAL4 Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk 6.06 (2) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI1, DPI2, DPI3 3.55 6.61 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI1, DPI2, DPI3 3.55 6.61 ns
  1. P = output vouti_clk period in ns.
  2. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 SWPS049-018.gifFigure 7-6 DPI Video Output(1)(2)(3)
  1. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
  2. The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
  3. The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-3 and described in Device TRM, Chapter 18 - Control Module.

In Table 7-19 are presented the specific groupings of signals (IOSET) for use with VOUT2.

Table 7-19 VOUT2 IOSETs

SIGNALS IOSET1 IOSET2
BALL MUX BALL MUX
vout2_d23 F2 4 AA4 6
vout2_d22 F3 4 AB3 6
vout2_d21 D1 4 AB9 6
vout2_d20 E2 4 AA3 6
vout2_d19 D2 4 D17 6
vout2_d18 F4 4 G16 6
vout2_d17 C1 4 A21 6
vout2_d16 E4 4 C18 6
vout2_d15 F5 4 A17 6
vout2_d14 E6 4 B17 6
vout2_d13 D3 4 B16 6
vout2_d12 F6 4 D15 6
vout2_d11 D5 4 A15 6
vout2_d10 C2 4 B15 6
vout2_d9 C3 4 A20 6
vout2_d8 C4 4 E15 6
vout2_d7 B2 4 D12 6
vout2_d6 D6 4 C12 6
vout2_d5 C5 4 F13 6
vout2_d4 A3 4 E12 6
vout2_d3 B3 4 J11 6
vout2_d2 B4 4 G13 6
vout2_d1 B5 4 J14 6
vout2_d0 A4 4 B14 6
vout2_vsync G6 4 F20 6
vout2_hsync G1 4 E21 6
vout2_clk H7 4 B26 6
vout2_fld E1 4 F21 6
vout2_de G2 4 C23 6

In Table 7-20 are presented the specific groupings of signals (IOSET) for use with VOUT3.

Table 7-20 VOUT3 IOSETs

SIGNALS IOSET1 IOSET2 (1) IOSET3 (1)
BALL MUX BALL MUX BALL MUX
vout3_d23 P5 3 AE8 4
vout3_d22 R5 3 AD8 4
vout3_d21 R9 3 AG7 4
vout3_d20 P6 3 AH6 4
vout3_d19 T7 3 AH3 4
vout3_d18 T6 3 AH5 4
vout3_d17 T9 3 AG6 4 AD9 3
vout3_d16 R6 3 AH4 4 AG8 3
vout3_d15 H3 3 AG4 4 AG4 4
vout3_d14 H2 3 AG2 4 AG2 4
vout3_d13 J3 3 AG3 4 AG3 4
vout3_d12 H1 3 AG5 4 AG5 4
vout3_d11 J2 3 AF2 4 AF2 4
vout3_d10 J1 3 AF6 4 AF6 4
vout3_d9 K2 3 AF3 4 AF3 4
vout3_d8 L1 3 AF4 4 AF4 4
vout3_d7 L2 3 AF1 4 AE8 3
vout3_d6 L3 3 AE3 4 AD8 3
vout3_d5 L4 3 AE5 4 AG7 3
vout3_d4 L6 3 AE1 4 AH6 3
vout3_d3 M1 3 AE2 4 AH3 3
vout3_d2 L5 3 AE6 4 AH5 3
vout3_d1 M2 3 AD2 4 AG6 3
vout3_d0 M6 3 AD3 4 AH4 3
vout3_de N9 3 AD9 4
vout3_vsync R4 3 AF8 4 AF8 4
vout3_clk P1 3 AF9 4 AF9 4
vout3_hsync N7 3 AE9 4 AE9 4
vout3_fld P9 3 AG8 4
  1. The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (VDDSHV6 must be supplied with 1.8V). 3.3V mode is not supported. This must be considered in the pin mux programming and VDDSHVx supply connections.

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to ensure some IO timings for VOUT1. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-21Manual Functions Mapping for DSS VOUT1 for a definition of the Manual modes.

Table 7-21 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-21 Manual Functions Mapping for DSS VOUT1

BALL BALL NAME VOUT1_MANUAL1 VOUT1_MANUAL2 VOUT1_MANUAL3 VOUT1_MANUAL4 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 0
D11 vout1_clk 0 706 1126 751 0 466 0 466 CFG_VOUT1_CLK_OUT vout1_clk
F11 vout1_d0 2313 0 395 0 3436 0 4306 0 CFG_VOUT1_D0_OUT vout1_d0
G10 vout1_d1 2439 0 521 0 3562 0 4432 0 CFG_VOUT1_D1_OUT vout1_d1
D7 vout1_d10 2199 0 282 0 3323 0 3993 0 CFG_VOUT1_D10_OUT vout1_d10
D8 vout1_d11 2266 0 348 0 3390 0 4060 0 CFG_VOUT1_D11_OUT vout1_d11
A5 vout1_d12 3159 0 1240 0 4281 0 4951 0 CFG_VOUT1_D12_OUT vout1_d12
C6 vout1_d13 2100 0 182 0 3223 0 4093 0 CFG_VOUT1_D13_OUT vout1_d13
C8 vout1_d14 2229 0 311 0 3353 0 4223 0 CFG_VOUT1_D14_OUT vout1_d14
C7 vout1_d15 2202 0 285 0 3326 0 4196 0 CFG_VOUT1_D15_OUT vout1_d15
B7 vout1_d16 2084 0 166 0 3208 0 4078 0 CFG_VOUT1_D16_OUT vout1_d16
B8 vout1_d17 2195 0 278 0 3319 0 4189 0 CFG_VOUT1_D17_OUT vout1_d17
A7 vout1_d18 2342 0 425 0 3466 0 4136 0 CFG_VOUT1_D18_OUT vout1_d18
A8 vout1_d19 2463 0 516 0 3557 0 4227 0 CFG_VOUT1_D19_OUT vout1_d19
F10 vout1_d2 2200 0 282 0 3324 0 4194 0 CFG_VOUT1_D2_OUT vout1_d2
C9 vout1_d20 2304 0 386 0 3428 0 4298 0 CFG_VOUT1_D20_OUT vout1_d20
A9 vout1_d21 2103 0 111 0 3193 0 4063 0 CFG_VOUT1_D21_OUT vout1_d21
B9 vout1_d22 2145 0 227 0 3268 0 4138 0 CFG_VOUT1_D22_OUT vout1_d22
A10 vout1_d23 1932 0 0 0 3039 0 3909 0 CFG_VOUT1_D23_OUT vout1_d23
G11 vout1_d3 2355 0 438 0 3479 0 4349 0 CFG_VOUT1_D3_OUT vout1_d3
E9 vout1_d4 3215 0 1298 0 4339 0 5209 0 CFG_VOUT1_D4_OUT vout1_d4
F9 vout1_d5 2314 0 397 0 3438 0 4308 0 CFG_VOUT1_D5_OUT vout1_d5
F8 vout1_d6 2238 0 321 0 3362 0 4082 0 CFG_VOUT1_D6_OUT vout1_d6
E7 vout1_d7 2381 0 155 309 3505 0 4175 0 CFG_VOUT1_D7_OUT vout1_d7
E8 vout1_d8 2138 0 212 0 3253 0 4123 0 CFG_VOUT1_D8_OUT vout1_d8
D9 vout1_d9 2383 0 466 0 3507 0 4377 0 CFG_VOUT1_D9_OUT vout1_d9
B10 vout1_de 1984 0 0 0 3085 0 3955 0 CFG_VOUT1_DE_OUT vout1_de
B11 vout1_fld 2265 0 236 0 3337 0 4207 0 CFG_VOUT1_FLD_OUT vout1_fld
C11 vout1_hsync 1947 0 0 0 3052 0 3922 0 CFG_VOUT1_HSYNC_OUT vout1_hsync
E11 vout1_vsync 2739 0 139 701 3863 0 4733 0 CFG_VOUT1_VSYNC_OUT vout1_vsync

Manual IO Timings Modes must be used to ensure some IO timings for VOUT2. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-22Manual Functions Mapping for DSS VOUT2 for a definition of the Manual modes.

Table 7-22 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-22 Manual Functions Mapping for DSS VOUT2 IOSET1

BALL BALL NAME VOUT2_IOSET1_MANUAL1 VOUT2_IOSET1_MANUAL2 VOUT2_IOSET1_MANUAL3 VOUT2_IOSET1_MANUAL4 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 4
E1 vin2a_clk0 2718 0 819 0 3794 0 4664 0 CFG_VIN2A_CLK0_OUT vout2_fld
F2 vin2a_d0 2680 0 485 296 3757 0 4627 0 CFG_VIN2A_D0_OUT vout2_d23
F3 vin2a_d1 2633 0 733 0 3710 0 4580 0 CFG_VIN2A_D1_OUT vout2_d22
D3 vin2a_d10 1867 0 0 0 2954 0 3824 0 CFG_VIN2A_D10_OUT vout2_d13
F6 vin2a_d11 2457 0 431 127 3534 0 4404 0 CFG_VIN2A_D11_OUT vout2_d12
D5 vin2a_d12 2683 1016 1286 514 3628 648 4498 648 CFG_VIN2A_D12_OUT vout2_d11
C2 vin2a_d13 2629 985 1229 486 3569 622 4439 622 CFG_VIN2A_D13_OUT vout2_d10
C3 vin2a_d14 2531 804 1126 309 3460 452 4530 452 CFG_VIN2A_D14_OUT vout2_d9
C4 vin2a_d15 2624 818 1227 315 3567 452 4537 452 CFG_VIN2A_D15_OUT vout2_d8
B2 vin2a_d16 2747 767 1357 256 3704 386 4574 386 CFG_VIN2A_D16_OUT vout2_d7
D6 vin2a_d17 2622 841 1226 337 3616 474 4686 474 CFG_VIN2A_D17_OUT vout2_d6
C5 vin2a_d18 2328 0 430 0 3406 0 4276 0 CFG_VIN2A_D18_OUT vout2_d5
A3 vin2a_d19 2300 0 401 0 3427 0 4197 0 CFG_VIN2A_D19_OUT vout2_d4
D1 vin2a_d2 2452 0 446 106 3528 0 4398 0 CFG_VIN2A_D2_OUT vout2_d21
B3 vin2a_d20 1998 0 98 0 3075 0 3845 0 CFG_VIN2A_D20_OUT vout2_d3
B4 vin2a_d21 1953 0 54 0 3030 0 3900 0 CFG_VIN2A_D21_OUT vout2_d2
B5 vin2a_d22 1893 0 0 0 3030 0 3900 0 CFG_VIN2A_D22_OUT vout2_d1
A4 vin2a_d23 1936 0 36 0 3013 0 3883 0 CFG_VIN2A_D23_OUT vout2_d0
E2 vin2a_d3 2494 0 595 0 3571 0 4441 0 CFG_VIN2A_D3_OUT vout2_d20
D2 vin2a_d4 3001 153 1254 0 4231 0 4901 0 CFG_VIN2A_D4_OUT vout2_d19
F4 vin2a_d5 2463 0 563 0 3539 0 4409 0 CFG_VIN2A_D5_OUT vout2_d18
C1 vin2a_d6 2456 0 558 0 3334 0 4404 0 CFG_VIN2A_D6_OUT vout2_d17
E4 vin2a_d7 2431 0 532 0 3509 0 4379 0 CFG_VIN2A_D7_OUT vout2_d16
F5 vin2a_d8 2262 0 363 0 3340 0 4210 0 CFG_VIN2A_D8_OUT vout2_d15
E6 vin2a_d9 2145 0 246 0 3222 0 4092 0 CFG_VIN2A_D9_OUT vout2_d14
G2 vin2a_de0 2597 0 550 149 3675 0 4545 0 CFG_VIN2A_DE0_OUT vout2_de
H7 vin2a_fld0 0 957 1208 969 0 686 0 686 CFG_VIN2A_FLD0_OUT vout2_clk
G1 vin2a_hsync0 2958 0 1059 0 4035 0 4905 0 CFG_VIN2A_HSYNC0_OUT vout2_hsync
G6 vin2a_vsync0 2752 0 853 0 3829 0 4699 0 CFG_VIN2A_VSYNC0_OUT vout2_vsync

Manual IO Timings Modes must be used to ensure some IO timings for VOUT2. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-23Manual Functions Mapping for DSS VOUT2 IOSET2 for a definition of the Manual modes.

Table 7-23 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-23 Manual Functions Mapping for DSS VOUT2 IOSET2

BALL BALL NAME VOUT2_IOSET2_MANUAL1 VOUT2_IOSET2_MANUAL2 VOUT2_IOSET2_MANUAL3 VOUT2_IOSET2_MANUAL4 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 6
E21 gpio6_14 1547 30 0 0 2298 0 3168 0 CFG_GPIO6_14_OUT vout2_hsync
F20 gpio6_15 1773 31 209 0 2484 0 3354 0 CFG_GPIO6_15_OUT vout2_vsync
F21 gpio6_16 1547 27 33 0 2345 0 3215 0 CFG_GPIO6_16_OUT vout2_fld
B14 mcasp1_aclkr 3738 2 2636 0 4925 0 5795 0 CFG_MCASP1_ACLKR_OUT vout2_d0
G13 mcasp1_axr2 2846 4 1730 0 4003 0 4873 0 CFG_MCASP1_AXR2_OUT vout2_d2
J11 mcasp1_axr3 2831 17 1498 0 3771 0 4541 0 CFG_MCASP1_AXR3_OUT vout2_d3
E12 mcasp1_axr4 3009 5 1879 0 4152 0 5022 0 CFG_MCASP1_AXR4_OUT vout2_d4
F13 mcasp1_axr5 3009 9 1802 0 4075 0 4945 0 CFG_MCASP1_AXR5_OUT vout2_d5
C12 mcasp1_axr6 2875 2 1792 0 4065 0 4935 0 CFG_MCASP1_AXR6_OUT vout2_d6
D12 mcasp1_axr7 2893 7 1717 0 3991 0 4861 0 CFG_MCASP1_AXR7_OUT vout2_d7
J14 mcasp1_fsr 2729 13 1466 0 3739 0 4609 0 CFG_MCASP1_FSR_OUT vout2_d1
E15 mcasp2_aclkr 3753 13 2488 0 4761 0 5631 0 CFG_MCASP2_ACLKR_OUT vout2_d8
B15 mcasp2_axr0 2182 6 1022 0 3294 0 4164 0 CFG_MCASP2_AXR0_OUT vout2_d10
A15 mcasp2_axr1 2324 5 1179 0 3452 0 4322 0 CFG_MCASP2_AXR1_OUT vout2_d11
D15 mcasp2_axr4 2434 0 1374 0 3647 0 4517 0 CFG_MCASP2_AXR4_OUT vout2_d12
B16 mcasp2_axr5 2287 4 1164 0 3437 0 4307 0 CFG_MCASP2_AXR5_OUT vout2_d13
B17 mcasp2_axr6 3598 13 2339 0 4599 0 5469 0 CFG_MCASP2_AXR6_OUT vout2_d14
A17 mcasp2_axr7 2231 15 931 0 3204 0 4074 0 CFG_MCASP2_AXR7_OUT vout2_d15
A20 mcasp2_fsr 1944 11 715 0 2988 0 3858 0 CFG_MCASP2_FSR_OUT vout2_d9
C18 mcasp4_aclkx 3241 8 2051 0 4324 0 5194 0 CFG_MCASP4_ACLKX_OUT vout2_d16
G16 mcasp4_axr0 2236 22 830 0 3090 0 3960 0 CFG_MCASP4_AXR0_OUT vout2_d18
D17 mcasp4_axr1 1803 16 505 0 2766 0 3636 0 CFG_MCASP4_AXR1_OUT vout2_d19
A21 mcasp4_fsx 1901 19 541 0 2801 0 3671 0 CFG_MCASP4_FSX_OUT vout2_d17
AA3 mcasp5_aclkx 4582 2178 3499 1978 6020 1755 6890 1755 CFG_MCASP5_ACLKX_OUT vout2_d20
AB3 mcasp5_axr0 4628 1604 3505 1402 6025 1178 6895 1178 CFG_MCASP5_AXR0_OUT vout2_d22
AA4 mcasp5_axr1 4757 1237 3457 1063 5987 806 6857 806 CFG_MCASP5_AXR1_OUT vout2_d23
AB9 mcasp5_fsx 4683 1485 3443 1280 5961 1059 6831 1059 CFG_MCASP5_FSX_OUT vout2_d21
B26 xref_clk2 0 850 1900 1150 0 730 0 730 CFG_XREF_CLK2_OUT vout2_clk
C23 xref_clk3 3075 19 1752 0 4012 0 4882 0 CFG_XREF_CLK3_OUT vout2_de

Manual IO Timings Modes must be used to ensure some IO timings for VOUT3. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-24Manual Functions Mapping for DSS VOUT3 for a definition of the Manual modes.

Table 7-24 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-24 Manual Functions Mapping for DSS VOUT3

BALL BALL NAME VOUT3_MANUAL1 VOUT3_MANUAL2 VOUT3_MANUAL3 VOUT3_MANUAL4 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 3 4
R6 gpmc_a0 3069 0 565 267 3365 0 4235 0 CFG_GPMC_A0_OUT vout3_d16 -
T9 gpmc_a1 2888 0 650 0 3183 0 4053 0 CFG_GPMC_A1_OUT vout3_d17 -
N9 gpmc_a10 3595 0 1157 0 3690 0 4560 0 CFG_GPMC_A10_OUT vout3_de -
P9 gpmc_a11 3891 14 669 970 4170 0 5040 0 CFG_GPMC_A11_OUT vout3_fld -
T6 gpmc_a2 2934 0 705 0 3238 0 4108 0 CFG_GPMC_A2_OUT vout3_d18 -
T7 gpmc_a3 3944 4 1521 0 4054 0 4924 0 CFG_GPMC_A3_OUT vout3_d19 -
P6 gpmc_a4 4456 261 1837 0 4370 0 5240 0 CFG_GPMC_A4_OUT vout3_d20 -
R9 gpmc_a5 2915 0 739 0 3273 0 4143 0 CFG_GPMC_A5_OUT vout3_d21 -
R5 gpmc_a6 3192 0 937 0 3471 0 4341 0 CFG_GPMC_A6_OUT vout3_d22 -
P5 gpmc_a7 3182 0 944 0 3477 0 4347 0 CFG_GPMC_A7_OUT vout3_d23 -
N7 gpmc_a8 4124 75 1843 0 4375 0 5245 0 CFG_GPMC_A8_OUT vout3_hsync -
R4 gpmc_a9 4252 0 998 0 3530 0 4400 0 CFG_GPMC_A9_OUT vout3_vsync -
M6 gpmc_ad0 3501 52 1151 0 3684 0 4534 0 CFG_GPMC_AD0_OUT vout3_d0 -
M2 gpmc_ad1 3163 0 956 0 3489 0 4339 0 CFG_GPMC_AD1_OUT vout3_d1 -
J1 gpmc_ad10 3130 0 1064 0 3598 0 4148 0 CFG_GPMC_AD10_OUT vout3_d10 -
J2 gpmc_ad11 2821 0 809 0 3344 0 3894 0 CFG_GPMC_AD11_OUT vout3_d11 -
H1 gpmc_ad12 3290 0 1161 0 3694 0 4244 0 CFG_GPMC_AD12_OUT vout3_d12 -
J3 gpmc_ad13 2573 0 524 0 3058 0 3908 0 CFG_GPMC_AD13_OUT vout3_d13 -
H2 gpmc_ad14 2540 0 632 0 3165 0 3715 0 CFG_GPMC_AD14_OUT vout3_d14 -
H3 gpmc_ad15 3181 0 1012 0 3545 0 4295 0 CFG_GPMC_AD15_OUT vout3_d15 -
L5 gpmc_ad2 3550 45 1222 0 3756 0 4506 0 CFG_GPMC_AD2_OUT vout3_d2 -
M1 gpmc_ad3 2922 0 875 0 3408 0 4158 0 CFG_GPMC_AD3_OUT vout3_d3 -
L6 gpmc_ad4 3463 36 1170 0 3703 0 4453 0 CFG_GPMC_AD4_OUT vout3_d4 -
L4 gpmc_ad5 2299 17 358 0 2930 0 3780 0 CFG_GPMC_AD5_OUT vout3_d5 -
L3 gpmc_ad6 3346 0 1184 0 3717 0 4267 0 CFG_GPMC_AD6_OUT vout3_d6 -
L2 gpmc_ad7 2971 0 908 0 3441 0 3991 0 CFG_GPMC_AD7_OUT vout3_d7 -
L1 gpmc_ad8 874 234 0 0 1923 0 2873 0 CFG_GPMC_AD8_OUT vout3_d8 -
K2 gpmc_ad9 1160 221 0 0 2402 0 3252 0 CFG_GPMC_AD9_OUT vout3_d9 -
P1 gpmc_cs3 0 600 1505 1379 0 947 0 947 CFG_GPMC_CS3_OUT vout3_clk -
AG8 vin1a_clk0 2670 0 1280 0 3511 0 4381 0 CFG_VIN1A_CLK0_OUT vout3_d16 vout3_fld
AE8 vin1a_d0 2750 196 1286 0 3820 0 4690 0 CFG_VIN1A_D0_OUT vout3_d7 vout3_d23
AD8 vin1a_d1 2409 240 1282 0 3816 0 4686 0 CFG_VIN1A_D1_OUT vout3_d6 vout3_d22
AG3 vin1a_d10 3026 270 1038 622 4228 0 5098 0 CFG_VIN1A_D10_OUT - vout3_d13
AG5 vin1a_d11 2711 203 1141 0 3867 0 4737 0 CFG_VIN1A_D11_OUT - vout3_d12
AF2 vin1a_d12 2924 539 1154 0 4422 0 5292 0 CFG_VIN1A_D12_OUT - vout3_d11
AF6 vin1a_d13 2861 235 1339 0 3815 0 4685 0 CFG_VIN1A_D13_OUT - vout3_d10
AF3 vin1a_d14 3176 377 892 0 4559 0 5429 0 CFG_VIN1A_D14_OUT - vout3_d9
AF4 vin1a_d15 2806 232 1221 89 3755 0 4625 0 CFG_VIN1A_D15_OUT - vout3_d8
AF1 vin1a_d16 2402 396 692 0 3873 0 4743 0 CFG_VIN1A_D16_OUT - vout3_d7
AE3 vin1a_d17 2132 374 353 0 3860 0 4730 0 CFG_VIN1A_D17_OUT - vout3_d6
AE5 vin1a_d18 2547 284 1109 0 3857 0 4727 0 CFG_VIN1A_D18_OUT - vout3_d5
AE1 vin1a_d19 2095 575 640 180 3929 0 4799 0 CFG_VIN1A_D19_OUT - vout3_d4
AG7 vin1a_d2 2546 189 1273 0 3806 0 4476 0 CFG_VIN1A_D2_OUT vout3_d5 vout3_d21
AE2 vin1a_d20 1825 735 628 0 3552 0 4622 0 CFG_VIN1A_D20_OUT - vout3_d3
AE6 vin1a_d21 2720 210 1322 0 4021 0 4891 0 CFG_VIN1A_D21_OUT - vout3_d2
AD2 vin1a_d22 2361 413 746 0 3659 0 4729 0 CFG_VIN1A_D22_OUT - vout3_d1
AD3 vin1a_d23 2731 273 1547 0 3775 0 4845 0 CFG_VIN1A_D23_OUT - vout3_d0
AH6 vin1a_d3 2534 219 1357 0 3890 0 4760 0 CFG_VIN1A_D3_OUT vout3_d4 vout3_d20
AH3 vin1a_d4 3015 538 2033 19 4585 0 5455 0 CFG_VIN1A_D4_OUT vout3_d3 vout3_d19
AH5 vin1a_d5 2451 237 1039 0 3572 0 4442 0 CFG_VIN1A_D5_OUT vout3_d2 vout3_d18
AG6 vin1a_d6 2505 191 1230 0 3763 0 4433 0 CFG_VIN1A_D6_OUT vout3_d1 vout3_d17
AH4 vin1a_d7 2550 170 1235 0 3768 0 4638 0 CFG_VIN1A_D7_OUT vout3_d0 vout3_d16
AG4 vin1a_d8 2847 285 1219 0 3850 0 4720 0 CFG_VIN1A_D8_OUT - vout3_d15
AG2 vin1a_d9 2857 247 1113 256 3900 0 4770 0 CFG_VIN1A_D9_OUT - vout3_d14
AD9 vin1a_de0 3164 0 1494 0 3728 0 4848 0 CFG_VIN1A_DE0_OUT vout3_d17 vout3_de
AF9 vin1a_fld0 0 1100 1718 869 261 384 261 384 CFG_VIN1A_FLD0_OUT - vout3_clk
AE9 vin1a_hsync0 3171 41 1439 0 3798 0 4668 0 CFG_VIN1A_HSYNC0_OUT - vout3_hsync
AF8 vin1a_vsync0 2956 110 1268 88 3610 0 4480 0 CFG_VIN1A_VSYNC0_OUT - vout3_vsync