JAJSFD3 データシート

JAJSFD3G August 2016 – March 2019 DRA780 , DRA781 , DRA782 , DRA783 , DRA785 , DRA786 , DRA787 , DRA788

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4.3.8 EMIF

NOTE

For more information, see the Memory Subsystem / EMIF Controller section of the Device TRM.

NOTE

The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Table 4-9, EMIF Signal Descriptions, column "SIGNAL NAME" is not to be confused with DDR1 type of SDRAM memories.

Table 4-9 EMIF Signal Descriptions

SIGNAL NAME	DESCRIPTION	TYPE	BALL
ddr1_cke0	EMIF1 Clock Enable 0	O	F3
ddr1_nck	EMIF1 Negative Clock	O	G2
ddr1_odt0	EMIF1 On-Die Termination for Chip Select 0	O	P2
ddr1_rasn	EMIF1 Row Address Strobe	O	F1
ddr1_rst	EMIF1 Reset output	O	N1
ddr1_wen	EMIF1 Write Enable	O	E3
ddr1_csn0	EMIF1 Chip Select 0	O	B2
ddr1_ck	EMIF1 Clock	O	G1
ddr1_casn	EMIF1 Column Address Strobe	O	F2
ddr1_ba0	EMIF1 Bank Address	O	B3
ddr1_ba1	EMIF1 Bank Address	O	A3
ddr1_ba2	EMIF1 Bank Address	O	D2
ddr1_a0	EMIF1 Address Bus	O	U4
ddr1_a1	EMIF1 Address Bus	O	C1
ddr1_a2	EMIF1 Address Bus	O	D3
ddr1_a3	EMIF1 Address Bus	O	R4
ddr1_a4	EMIF1 Address Bus	O	T4
ddr1_a5	EMIF1 Address Bus	O	N3
ddr1_a6	EMIF1 Address Bus	O	T2
ddr1_a7	EMIF1 Address Bus	O	N2
ddr1_a8	EMIF1 Address Bus	O	T1
ddr1_a9	EMIF1 Address Bus	O	U1
ddr1_a10	EMIF1 Address Bus	O	D1
ddr1_a11	EMIF1 Address Bus	O	R3
ddr1_a12	EMIF1 Address Bus	O	U2
ddr1_a13	EMIF1 Address Bus	O	C3
ddr1_a14	EMIF1 Address Bus	O	R2
ddr1_a15	EMIF1 Address Bus	O	V1
ddr1_d0	EMIF1 Data Bus	IO	AA6
ddr1_d1	EMIF1 Data Bus	IO	AA8
ddr1_d2	EMIF1 Data Bus	IO	Y8
ddr1_d3	EMIF1 Data Bus	IO	AA7
ddr1_d4	EMIF1 Data Bus	IO	AB4
ddr1_d5	EMIF1 Data Bus	IO	Y5
ddr1_d6	EMIF1 Data Bus	IO	AA4
ddr1_d7	EMIF1 Data Bus	IO	Y6
ddr1_d8	EMIF1 Data Bus	IO	AA18
ddr1_d9	EMIF1 Data Bus	IO	Y21
ddr1_d10	EMIF1 Data Bus	IO	AA21
ddr1_d11	EMIF1 Data Bus	IO	Y22
ddr1_d12	EMIF1 Data Bus	IO	AA19
ddr1_d13	EMIF1 Data Bus	IO	AB20
ddr1_d14	EMIF1 Data Bus	IO	Y17
ddr1_d15	EMIF1 Data Bus	IO	AB18
ddr1_d16	EMIF1 Data Bus	IO	AA3
ddr1_d17	EMIF1 Data Bus	IO	AA2
ddr1_d18	EMIF1 Data Bus	IO	Y3
ddr1_d19	EMIF1 Data Bus	IO	V2
ddr1_d20	EMIF1 Data Bus	IO	U3
ddr1_d21	EMIF1 Data Bus	IO	V3
ddr1_d22	EMIF1 Data Bus	IO	Y2
ddr1_d23	EMIF1 Data Bus	IO	Y1
ddr1_d24	EMIF1 Data Bus	IO	U21
ddr1_d25	EMIF1 Data Bus	IO	T20
ddr1_d26	EMIF1 Data Bus	IO	R21
ddr1_d27	EMIF1 Data Bus	IO	U20
ddr1_d28	EMIF1 Data Bus	IO	R22
ddr1_d29	EMIF1 Data Bus	IO	V20
ddr1_d30	EMIF1 Data Bus	IO	W22
ddr1_d31	EMIF1 Data Bus	IO	U22
ddr1_ecc_d0	EMIF1 ECC Data Bus	IO	Y11
ddr1_ecc_d1	EMIF1 ECC Data Bus	IO	AA12
ddr1_ecc_d2	EMIF1 ECC Data Bus	IO	AA11
ddr1_ecc_d3	EMIF1 ECC Data Bus	IO	Y9
ddr1_ecc_d4	EMIF1 ECC Data Bus	IO	AA13
ddr1_ecc_d5	EMIF1 ECC Data Bus	IO	AB11
ddr1_ecc_d6	EMIF1 ECC Data Bus	IO	AA9
ddr1_ecc_d7	EMIF1 ECC Data Bus	IO	AB9
ddr1_dqm0	EMIF1 Data Mask	IO	AB8
ddr1_dqm1	EMIF1 Data Mask	IO	Y18
ddr1_dqm2	EMIF1 Data Mask	IO	AB3
ddr1_dqm3	EMIF1 Data Mask	IO	W21
ddr1_dqm_ecc	EMIF1 ECC Data Mask	IO	AB13
ddr1_dqs0	Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AA5
ddr1_dqs1	Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AA20
ddr1_dqs2	Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	W1
ddr1_dqs3	Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading.	IO	T21
ddr1_dqsn0	Data strobe 0 invert	IO	AB5
ddr1_dqsn1	Data strobe 1 invert	IO	Y20
ddr1_dqsn2	Data strobe 2 invert	IO	W2
ddr1_dqsn3	Data strobe 3 invert	IO	T22
ddr1_dqsn_ecc	EMIF1 ECC Complementary Data strobe	IO	AB10
ddr1_dqs_ecc	EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when writing and input when reading.	IO	AA10