JAJSFD3G August   2016  – March 2019 DRA780 , DRA781 , DRA782 , DRA783 , DRA785 , DRA786 , DRA787 , DRA788

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  SD_DAC
      4. 4.3.4  ADC
      5. 4.3.5  Camera Control
      6. 4.3.6  CPI
      7. 4.3.7  CSI2
      8. 4.3.8  EMIF
      9. 4.3.9  GPMC
      10. 4.3.10 Timers
      11. 4.3.11 I2C
      12. 4.3.12 UART
      13. 4.3.13 McSPI
      14. 4.3.14 QSPI
      15. 4.3.15 McASP
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 SDIO Controller
      19. 4.3.19 GPIO
      20. 4.3.20 ePWM
      21. 4.3.21 ATL
      22. 4.3.22 Test Interfaces
      23. 4.3.23 System and Miscellaneous
        1. 4.3.23.1 Sysboot
        2. 4.3.23.2 Power, Reset and Clock Management (PRCM)
        3. 4.3.23.3 Enhanced Direct Memory Access (EDMA)
        4. 4.3.23.4 Interrupt Controllers (INTC)
      24. 4.3.24 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS Analog OSC Buffers DC Electrical Characteristics
      6. Table 5-11 Dual Voltage LVCMOS DC Electrical Characteristics
      7. Table 5-12 Analog-to-Digital ADC Subsystem Electrical Specifications
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Timing Requirements and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
        1. 5.9.1.1 Parameter Information
          1. 5.9.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.9.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.9.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.9.2 Interface Clock Specifications
        1. 5.9.2.1 Interface Clock Terminology
        2. 5.9.2.2 Interface Clock Frequency
      3. 5.9.3 Power Supply Sequences
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 OSC0 External Crystal
          2. 5.9.4.1.2 OSC0 Input Clock
          3. 5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.9.4.1.3.1 OSC1 External Crystal
            2. 5.9.4.1.3.2 OSC1 Input Clock
          4. 5.9.4.1.4 RC On-die Oscillator Clock
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 DPLLs, DLLs
          1. 5.9.4.3.1 DPLL Characteristics
          2. 5.9.4.3.2 DLL Characteristics
            1. 5.9.4.3.2.1 DPLL and DLL Noise Isolation
      5. 5.9.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.9.6 Peripherals
        1. 5.9.6.1  Timing Test Conditions
        2. 5.9.6.2  VIP
        3. 5.9.6.3  DSS
        4. 5.9.6.4  EMIF
        5. 5.9.6.5  GPMC
          1. 5.9.6.5.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.9.6.5.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.9.6.5.3 GPMC/NAND Flash Interface Asynchronous Timing
        6. 5.9.6.6  GP Timers
          1. 5.9.6.6.1 GP Timer Features
        7. 5.9.6.7  I2C
          1. Table 5-39 Timing Requirements for I2C Input Timings
          2. Table 5-40 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        8. 5.9.6.8  UART
          1. Table 5-41 Timing Requirements for UART
          2. Table 5-42 Switching Characteristics Over Recommended Operating Conditions for UART
        9. 5.9.6.9  McSPI
        10. 5.9.6.10 QSPI
        11. 5.9.6.11 McASP
          1. Table 5-50 Timing Requirements for McASP1
          2. Table 5-51 Timing Requirements for McASP2
          3. Table 5-52 Timing Requirements for McASP3
          4. Table 5-53 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-54 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-55 Switching Characteristics Over Recommended Operating Conditions for McASP3
        12. 5.9.6.12 DCAN and MCAN
          1. 5.9.6.12.1 DCAN
          2. 5.9.6.12.2 MCAN
          3. Table 5-58 Timing Requirements for CAN Receive
          4. Table 5-59 Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
        13. 5.9.6.13 GMAC_SW
          1. 5.9.6.13.1 GMAC MDIO Interface Timings
          2. 5.9.6.13.2 GMAC RGMII Timings
            1. Table 5-63 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-64 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-65 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-66 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        14. 5.9.6.14 SDIO Controller
          1. 5.9.6.14.1 MMC, SD Default Speed
          2. 5.9.6.14.2 MMC, SD High Speed
          3. 5.9.6.14.3 MMC, SD and SDIO SDR12 Mode
          4. 5.9.6.14.4 MMC, SD SDR25 Mode
        15. 5.9.6.15 GPIO
        16. 5.9.6.16 ATL
          1. 5.9.6.16.1 ATL Electrical Data/Timing
            1. Table 5-77 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
      7. 5.9.7 Emulation and Debug Subsystem
        1. 5.9.7.1 JTAG Electrical Data/Timing
          1. Table 5-78 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 5-79 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 5-80 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 5-81 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.9.7.2 Trace Port Interface Unit (TPIU)
          1. 5.9.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  DSP Subsystem
    4. 6.4  IPU
    5. 6.5  EVE
    6. 6.6  Memory Subsystem
      1. 6.6.1 EMIF
      2. 6.6.2 GPMC
      3. 6.6.3 ELM
      4. 6.6.4 OCMC
    7. 6.7  Interprocessor Communication
      1. 6.7.1 Mailbox
      2. 6.7.2 Spinlock
    8. 6.8  Interrupt Controller
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  VIP
      2. 6.10.2  DSS
      3. 6.10.3  ATL
      4. 6.10.4  ADC
      5. 6.10.5  Timers
        1. 6.10.5.1 General-Purpose Timers
        2. 6.10.5.2 32-kHz Synchronized Timer (COUNTER_32K)
      6. 6.10.6  I2C
      7. 6.10.7  UART
        1. 6.10.7.1 UART Features
      8. 6.10.8  McSPI
      9. 6.10.9  QSPI
      10. 6.10.10 McASP
      11. 6.10.11 DCAN
      12. 6.10.12 MCAN
      13. 6.10.13 GMAC_SW
      14. 6.10.14 SDIO
      15. 6.10.15 GPIO
      16. 6.10.16 ePWM
      17. 6.10.17 eCAP
      18. 6.10.18 eQEP
    11. 6.11 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_dspeve Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
        1. 7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR2 Board Design and Layout Guidelines
      1. 7.7.1 DDR2 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High-Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
    8. 7.8 DDR3 Board Design and Layout Guidelines
      1. 7.8.1 DDR3 General Board Layout Guidelines
      2. 7.8.2 DDR3 Board Design and Layout Guidelines
        1. 7.8.2.1  Board Designs
        2. 7.8.2.2  DDR3 Device Combinations
        3. 7.8.2.3  DDR3 Interface Schematic
          1. 7.8.2.3.1 32-Bit DDR3 Interface
          2. 7.8.2.3.2 16-Bit DDR3 Interface
        4. 7.8.2.4  Compatible JEDEC DDR3 Devices
        5. 7.8.2.5  PCB Stackup
        6. 7.8.2.6  Placement
        7. 7.8.2.7  DDR3 Keepout Region
        8. 7.8.2.8  Bulk Bypass Capacitors
        9. 7.8.2.9  High-Speed Bypass Capacitors
          1. 7.8.2.9.1 Return Current Bypass Capacitors
        10. 7.8.2.10 Net Classes
        11. 7.8.2.11 DDR3 Signal Termination
        12. 7.8.2.12 VTT
        13. 7.8.2.13 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.8.2.13.1 Three DDR3 Devices
            1. 7.8.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 7.8.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 7.8.2.13.2 Two DDR3 Devices
            1. 7.8.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.8.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.8.2.13.3 One DDR3 Device
            1. 7.8.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.8.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        14. 7.8.2.14 Data Topologies and Routing Definition
          1. 7.8.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.8.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 7.8.2.15 Routing Specification
          1. 7.8.2.15.1 CK and ADDR_CTRL Routing Specification
          2. 7.8.2.15.2 DQS and DQ Routing Specification
    9. 7.9 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABF|367
サーマルパッド・メカニカル・データ
発注情報

4.3.19 GPIO

NOTE

For more information, see the General-Purpose Interface section of the Device TRM.

CAUTION

The IO timings provided in Section 5.9, Timing Requirements and Switching Characteristics are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-76.

Table 4-20 GPIOs Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
GPIO 1
gpio1_0 General-Purpose Input/Output IO C12
gpio1_1 General-Purpose Input/Output IO D12
gpio1_2 General-Purpose Input/Output IO E12
gpio1_3 General-Purpose Input/Output IO F12
gpio1_4 General-Purpose Input/Output IO A10
gpio1_5 General-Purpose Input/Output IO B10
gpio1_6 General-Purpose Input/Output IO C10
gpio1_7 General-Purpose Input/Output IO E10
gpio1_8 General-Purpose Input/Output IO D10
gpio1_9 General-Purpose Input/Output IO A9
gpio1_10 General-Purpose Input/Output IO B9
gpio1_11 General-Purpose Input/Output IO F10
gpio1_12 General-Purpose Input/Output IO C8
gpio1_13 General-Purpose Input/Output IO D8
gpio1_14 General-Purpose Input/Output IO E8
gpio1_15 General-Purpose Input/Output IO A7
gpio1_16 General-Purpose Input/Output IO F8
gpio1_17 General-Purpose Input/Output IO B7
gpio1_18 General-Purpose Input/Output IO A6
gpio1_19 General-Purpose Input/Output IO F7
gpio1_20 General-Purpose Input/Output IO E7
gpio1_21 General-Purpose Input/Output IO C6
gpio1_22 General-Purpose Input/Output IO B6
gpio1_23 General-Purpose Input/Output IO A5
gpio1_24 General-Purpose Input/Output IO D6
gpio1_25 General-Purpose Input/Output IO C5
gpio1_26 General-Purpose Input/Output IO B5
gpio1_27 General-Purpose Input/Output IO D7
gpio1_28 General-Purpose Input/Output IO B4
gpio1_29 General-Purpose Input/Output IO A4
gpio1_30 General-Purpose Input/Output IO F22
gpio1_31 General-Purpose Input/Output IO F21
GPIO 2
gpio2_0 General-Purpose Input/Output IO F20
gpio2_1 General-Purpose Input/Output IO F19
gpio2_2 General-Purpose Input/Output IO G19
gpio2_3 General-Purpose Input/Output IO G18
gpio2_4 General-Purpose Input/Output IO G21
gpio2_5 General-Purpose Input/Output IO G22
gpio2_6 General-Purpose Input/Output IO H18
gpio2_7 General-Purpose Input/Output IO H20
gpio2_8 General-Purpose Input/Output IO H19
gpio2_9 General-Purpose Input/Output IO H22
gpio2_10 General-Purpose Input/Output IO H21
gpio2_11 General-Purpose Input/Output IO J17
gpio2_12 General-Purpose Input/Output IO K22
gpio2_13 General-Purpose Input/Output IO K21
gpio2_14 General-Purpose Input/Output IO K18
gpio2_15 General-Purpose Input/Output IO K17
gpio2_16 General-Purpose Input/Output IO K19
gpio2_17 General-Purpose Input/Output IO K20
gpio2_18 General-Purpose Input/Output IO L21
gpio2_19 General-Purpose Input/Output IO L22
gpio2_20 General-Purpose Input/Output IO AB17
gpio2_21 General-Purpose Input/Output IO U17
gpio2_22 General-Purpose Input/Output IO W17
gpio2_23 General-Purpose Input/Output IO AA17
gpio2_24 General-Purpose Input/Output IO U16
gpio2_25 General-Purpose Input/Output IO W16
gpio2_26 General-Purpose Input/Output IO V16
gpio2_27 General-Purpose Input/Output IO U15
gpio2_28 General-Purpose Input/Output IO V15
gpio2_29 General-Purpose Input/Output IO Y15
gpio2_30 General-Purpose Input/Output IO W15
gpio2_31 General-Purpose Input/Output IO AA15
GPIO 3
gpio3_0 General-Purpose Input/Output IO AB15
gpio3_1 General-Purpose Input/Output IO AA14
gpio3_2 General-Purpose Input/Output IO AB14
gpio3_3 General-Purpose Input/Output IO U13
gpio3_4 General-Purpose Input/Output IO V13
gpio3_5 General-Purpose Input/Output IO Y13
gpio3_6 General-Purpose Input/Output IO W13
gpio3_7 General-Purpose Input/Output IO U11
gpio3_8 General-Purpose Input/Output IO V11
gpio3_9 General-Purpose Input/Output IO U9
gpio3_10 General-Purpose Input/Output IO W11
gpio3_11 General-Purpose Input/Output IO V9
gpio3_12 General-Purpose Input/Output IO W9
gpio3_13 General-Purpose Input/Output IO U8
gpio3_14 General-Purpose Input/Output IO W8
gpio3_15 General-Purpose Input/Output IO U7
gpio3_16 General-Purpose Input/Output IO V7
gpio3_17 General-Purpose Input/Output IO B19
gpio3_18 General-Purpose Input/Output IO B17
gpio3_19 General-Purpose Input/Output IO C16
gpio3_20 General-Purpose Input/Output IO C17
gpio3_21 General-Purpose Input/Output IO E16
gpio3_22 General-Purpose Input/Output IO D16
gpio3_23 General-Purpose Input/Output IO E17
gpio3_24 General-Purpose Input/Output IO F17
gpio3_25 General-Purpose Input/Output IO B18
gpio3_26 General-Purpose Input/Output IO C18
gpio3_27 General-Purpose Input/Output IO A19
gpio3_28 General-Purpose Input/Output IO B20
gpio3_29 General-Purpose Input/Output IO C20
gpio3_30 General-Purpose Input/Output IO A20
gpio3_31 General-Purpose Input/Output IO M1
GPIO 4
gpio4_0 General-Purpose Input/Output IO M2
gpio4_1 General-Purpose Input/Output IO U6
gpio4_2 General-Purpose Input/Output IO T5
gpio4_3 General-Purpose Input/Output IO R6
gpio4_4 General-Purpose Input/Output IO R5
gpio4_5 General-Purpose Input/Output IO L1
gpio4_6 General-Purpose Input/Output IO N4
gpio4_7 General-Purpose Input/Output IO R7
gpio4_8 General-Purpose Input/Output IO L2
gpio4_9 General-Purpose Input/Output IO N5
gpio4_10 General-Purpose Input/Output IO N6
gpio4_11 General-Purpose Input/Output IO W7
gpio4_12 General-Purpose Input/Output IO W6
gpio4_13 General-Purpose Input/Output IO F13
gpio4_14 General-Purpose Input/Output IO E14
gpio4_15 General-Purpose Input/Output IO F14
gpio4_16 General-Purpose Input/Output IO C14
gpio4_17 General-Purpose Input/Output IO D14
gpio4_18 General-Purpose Input/Output IO D15
gpio4_19 General-Purpose Input/Output IO F15
gpio4_20 General-Purpose Input/Output IO F16
gpio4_21 General-Purpose Input/Output IO M17
gpio4_22 General-Purpose Input/Output IO M18
gpio4_25 General-Purpose Input/Output IO J1
gpio4_26 General-Purpose Input/Output IO J4
gpio4_27 General-Purpose Input/Output IO J6
gpio4_28(1) General-Purpose Input/Output IO H1
gpio4_29(1) General-Purpose Input/Output IO H2
  1. gpio4_28 is multiplexed with EMU0 and gpio4_29 is multiplexed with EMU1. These pins will be sampled at reset release by the test and emulation logic. Therefore, if they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can be controlled by logic driven from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.