JAJSFD3G August   2016  – March 2019 DRA780 , DRA781 , DRA782 , DRA783 , DRA785 , DRA786 , DRA787 , DRA788

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  SD_DAC
      4. 4.3.4  ADC
      5. 4.3.5  Camera Control
      6. 4.3.6  CPI
      7. 4.3.7  CSI2
      8. 4.3.8  EMIF
      9. 4.3.9  GPMC
      10. 4.3.10 Timers
      11. 4.3.11 I2C
      12. 4.3.12 UART
      13. 4.3.13 McSPI
      14. 4.3.14 QSPI
      15. 4.3.15 McASP
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 SDIO Controller
      19. 4.3.19 GPIO
      20. 4.3.20 ePWM
      21. 4.3.21 ATL
      22. 4.3.22 Test Interfaces
      23. 4.3.23 System and Miscellaneous
        1. 4.3.23.1 Sysboot
        2. 4.3.23.2 Power, Reset and Clock Management (PRCM)
        3. 4.3.23.3 Enhanced Direct Memory Access (EDMA)
        4. 4.3.23.4 Interrupt Controllers (INTC)
      24. 4.3.24 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS Analog OSC Buffers DC Electrical Characteristics
      6. Table 5-11 Dual Voltage LVCMOS DC Electrical Characteristics
      7. Table 5-12 Analog-to-Digital ADC Subsystem Electrical Specifications
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Timing Requirements and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
        1. 5.9.1.1 Parameter Information
          1. 5.9.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.9.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.9.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.9.2 Interface Clock Specifications
        1. 5.9.2.1 Interface Clock Terminology
        2. 5.9.2.2 Interface Clock Frequency
      3. 5.9.3 Power Supply Sequences
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 OSC0 External Crystal
          2. 5.9.4.1.2 OSC0 Input Clock
          3. 5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.9.4.1.3.1 OSC1 External Crystal
            2. 5.9.4.1.3.2 OSC1 Input Clock
          4. 5.9.4.1.4 RC On-die Oscillator Clock
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 DPLLs, DLLs
          1. 5.9.4.3.1 DPLL Characteristics
          2. 5.9.4.3.2 DLL Characteristics
            1. 5.9.4.3.2.1 DPLL and DLL Noise Isolation
      5. 5.9.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.9.6 Peripherals
        1. 5.9.6.1  Timing Test Conditions
        2. 5.9.6.2  VIP
        3. 5.9.6.3  DSS
        4. 5.9.6.4  EMIF
        5. 5.9.6.5  GPMC
          1. 5.9.6.5.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.9.6.5.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.9.6.5.3 GPMC/NAND Flash Interface Asynchronous Timing
        6. 5.9.6.6  GP Timers
          1. 5.9.6.6.1 GP Timer Features
        7. 5.9.6.7  I2C
          1. Table 5-39 Timing Requirements for I2C Input Timings
          2. Table 5-40 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        8. 5.9.6.8  UART
          1. Table 5-41 Timing Requirements for UART
          2. Table 5-42 Switching Characteristics Over Recommended Operating Conditions for UART
        9. 5.9.6.9  McSPI
        10. 5.9.6.10 QSPI
        11. 5.9.6.11 McASP
          1. Table 5-50 Timing Requirements for McASP1
          2. Table 5-51 Timing Requirements for McASP2
          3. Table 5-52 Timing Requirements for McASP3
          4. Table 5-53 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-54 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-55 Switching Characteristics Over Recommended Operating Conditions for McASP3
        12. 5.9.6.12 DCAN and MCAN
          1. 5.9.6.12.1 DCAN
          2. 5.9.6.12.2 MCAN
          3. Table 5-58 Timing Requirements for CAN Receive
          4. Table 5-59 Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
        13. 5.9.6.13 GMAC_SW
          1. 5.9.6.13.1 GMAC MDIO Interface Timings
          2. 5.9.6.13.2 GMAC RGMII Timings
            1. Table 5-63 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-64 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-65 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-66 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        14. 5.9.6.14 SDIO Controller
          1. 5.9.6.14.1 MMC, SD Default Speed
          2. 5.9.6.14.2 MMC, SD High Speed
          3. 5.9.6.14.3 MMC, SD and SDIO SDR12 Mode
          4. 5.9.6.14.4 MMC, SD SDR25 Mode
        15. 5.9.6.15 GPIO
        16. 5.9.6.16 ATL
          1. 5.9.6.16.1 ATL Electrical Data/Timing
            1. Table 5-77 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
      7. 5.9.7 Emulation and Debug Subsystem
        1. 5.9.7.1 JTAG Electrical Data/Timing
          1. Table 5-78 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 5-79 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 5-80 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 5-81 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.9.7.2 Trace Port Interface Unit (TPIU)
          1. 5.9.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  DSP Subsystem
    4. 6.4  IPU
    5. 6.5  EVE
    6. 6.6  Memory Subsystem
      1. 6.6.1 EMIF
      2. 6.6.2 GPMC
      3. 6.6.3 ELM
      4. 6.6.4 OCMC
    7. 6.7  Interprocessor Communication
      1. 6.7.1 Mailbox
      2. 6.7.2 Spinlock
    8. 6.8  Interrupt Controller
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  VIP
      2. 6.10.2  DSS
      3. 6.10.3  ATL
      4. 6.10.4  ADC
      5. 6.10.5  Timers
        1. 6.10.5.1 General-Purpose Timers
        2. 6.10.5.2 32-kHz Synchronized Timer (COUNTER_32K)
      6. 6.10.6  I2C
      7. 6.10.7  UART
        1. 6.10.7.1 UART Features
      8. 6.10.8  McSPI
      9. 6.10.9  QSPI
      10. 6.10.10 McASP
      11. 6.10.11 DCAN
      12. 6.10.12 MCAN
      13. 6.10.13 GMAC_SW
      14. 6.10.14 SDIO
      15. 6.10.15 GPIO
      16. 6.10.16 ePWM
      17. 6.10.17 eCAP
      18. 6.10.18 eQEP
    11. 6.11 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_dspeve Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
        1. 7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR2 Board Design and Layout Guidelines
      1. 7.7.1 DDR2 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High-Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
    8. 7.8 DDR3 Board Design and Layout Guidelines
      1. 7.8.1 DDR3 General Board Layout Guidelines
      2. 7.8.2 DDR3 Board Design and Layout Guidelines
        1. 7.8.2.1  Board Designs
        2. 7.8.2.2  DDR3 Device Combinations
        3. 7.8.2.3  DDR3 Interface Schematic
          1. 7.8.2.3.1 32-Bit DDR3 Interface
          2. 7.8.2.3.2 16-Bit DDR3 Interface
        4. 7.8.2.4  Compatible JEDEC DDR3 Devices
        5. 7.8.2.5  PCB Stackup
        6. 7.8.2.6  Placement
        7. 7.8.2.7  DDR3 Keepout Region
        8. 7.8.2.8  Bulk Bypass Capacitors
        9. 7.8.2.9  High-Speed Bypass Capacitors
          1. 7.8.2.9.1 Return Current Bypass Capacitors
        10. 7.8.2.10 Net Classes
        11. 7.8.2.11 DDR3 Signal Termination
        12. 7.8.2.12 VTT
        13. 7.8.2.13 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.8.2.13.1 Three DDR3 Devices
            1. 7.8.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 7.8.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 7.8.2.13.2 Two DDR3 Devices
            1. 7.8.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.8.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.8.2.13.3 One DDR3 Device
            1. 7.8.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.8.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        14. 7.8.2.14 Data Topologies and Routing Definition
          1. 7.8.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.8.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 7.8.2.15 Routing Specification
          1. 7.8.2.15.1 CK and ADDR_CTRL Routing Specification
          2. 7.8.2.15.2 DQS and DQ Routing Specification
    9. 7.9 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

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発注情報

5.5.3 Maximum Supported Frequency

Device modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM. Table 5-5 lists the clock source options for each module on this device, along with the maximum frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.

Table 5-5 Maximum Supported Frequency

Module Clock Sources
Instance Name Input Clock Name Clock Type Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name PLL / OSC / Source Name
ADC OCP_CLK Int 133 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
ADC_CLK Func 20 ADC_CLK SYS_CLK1 OSC0
SYS_CLK2 OSC1
XREF_CLK0 xref_clk0
ATL ATL_ICLK_L3 Int 266 ATL_L3_GICLK CORE_X2_CLK DPLL_CORE
ATLPCLK Func 266 ATL_GFCLK CORE_X2_CLK DPLL_CORE
FUNC_32K_CLK OSC1
RTC Oscillator
COUNTER_32K COUNTER_32K_FCLK Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC0
COUNTER_32K_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
CTRL_MODULE_BANDGAP L3INSTR_TS_GCLK Int 5 L3INSTR_TS_GCLK SYS_CLK1 OSC0
ABE_LP_CLK DPLL_DDR
CTRL_MODULE_CORE L4CFG_L4_GICLK Int 133 L4_ICLK CORE_X2_CLK DPLL_CORE
CTRL_MODULE_WKUP WKUPAON_GICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
ABE_LP_CLK DPLL_DDR
DCAN1 DCAN1_FCLK Func 20 DCAN1_SYS_CLK SYS_CLK1 OSC0
SYS_CLK2 OSC1
DCAN1_ICLK Int 133 WKUPAON_GICLK SYS_CLK1 OSC0
ABE_LP_CLK DPLL_DDR
MCAN MCAN_FCLK Func 80 MCAN_CLK MCAN_CLK DPLL_GMAC_DSP
MCAN_ICLK Int 133 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
DLL EMIF_DLL_FCLK Func 266 EMIF_DLL_GCLK EMIF_DLL_GCLK DPLL_DDR
DSP1 DSP1_FICLK Int & Func DSP_CLK DSP1_GFCLK DSP_GFCLK DPLL_EVE_VID_DSP
DPLL_CORE
DPLL_GMAC_DSP
DSP2 DSP2_FICLK Int & Func DSP_CLK DSP2_GFCLK DSP_GFCLK DPLL_EVE_VID_DSP
DPLL_CORE
DPLL_GMAC_DSP
DSS DSS_FCK_CLK Int & Func 192 DSS_GFCLK DSS_GFCLK DPLL_PER
DSS_VP_CLK Func 165 VID_PIX_CLK VID_PIX_CLK DPLL_EVE_VID_DSP
DSS DISPC DISPC_FCK_CLK Int & Func 192 DSS_GFCLK DSS_GFCLK DPLL_PER
DISPC_CLK1 Int 165 VID_PIX_CLK VID_PIX_CLK DPLL_EVE_VID_DSP
EFUSE_CTRL_CUST ocp_clk Int 133 CUSTEFUSE_L4_GICLK CORE_X2_CLK DPLL_CORE
sys_clk Func 38.4 CUSTEFUSE_SYS_GFCLK SYS_CLK1 OSC0
ELM ELM_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
EMIF_OCP_FW L3_CLK Int 266 EMIF_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_CLKEN Int 133 EMIF_L4_GICLK CORE_X2_CLK DPLL_CORE
EMIF_PHY EMIF_PHY_FCLK Func DDR EMIF_PHY_GCLK EMIF_PHY_GCLK DPLL_DDR
EMIF_DLL_FCLK Int 266 EMIF_DLL_GCLK - DPLL_DDR
EMIF EMIF_ICLK Int 266 EMIF_L3_GICLK CORE_X2_CLK DPLL_CORE
EMIF_L3_ICLK Int 266 L3_EOCP_GICLK - -
EMIF_FICLK Func DDR/2 EMIF_PHY_GCLK/2 EMIF_PHY_GCLK DPLL_DDR
EVE EVE_FCLK Func EVE_FCLK EVE_CLK EVE_GCLK DPLL_CORE
DPLL_GMAC_DSP
EVE_GFCLK DPLL_EVE_VID_DSP
GMAC_SW CPTS_RFT_CLK Func 266 GMAC_RFT_CLK L3_ICLK DPLL_CORE
SYS_CLK1 OSC0
MAIN_CLK Int 125 GMAC_MAIN_CLK GMAC_250M_CLK DPLL_GMAC_DSP
MHZ_250_CLK Func 250 GMII_250MHZ_CLK GMII_250MHZ_CLK DPLL_GMAC_DSP
MHZ_5_CLK Func 5 RGMII_5MHZ_CLK RMII_50MHZ_CLK/10 DPLL_GMAC_DSP
MHZ_50_CLK Func 50 RMII_50MHZ_CLK GMAC_RMII_HS_ CLK DPLL_GMAC_DSP
GPIO1 GPIO1_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
GPIO1_DBCLK Func 0.032 WKUPAON_32K_GFCLK SYS_CLK1/610 OSC0
GPIO2 GPIO2_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO2_DBCLK Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC0
GPIO3 GPIO3_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO3_DBCLK Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC0
GPIO4 GPIO4_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO4_DBCLK Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC0
GPMC GPMC_ICLK Int & Func 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
I2C1 I2C1_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
I2C1_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER
I2C2 I2C2_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
I2C2_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER
IEEE1500_2_OCP PI_L3CLK Int & Func 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE
IPU1 IPU1_GFCLK Int & Func IPU_CLK IPU1_GFCLK DPLL_ABE_X2_CLK DPLL_DDR
CORE_IPU_ISS_BOOST_CLK DPLL_CORE
L3_INSTR L3_CLK Int L3_CLK L3INSTR_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_CFG L4_CFG_CLK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_PER1 L4_PER1_CLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_PER2 L4_PER2_CLK Int 133 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_PER3 L4_PER3_CLK Int 133 L4PER3_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_WKUP L4_WKUP_CLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
ABE_LP_CLK DPLL_DDR
MAILBOX1 MAILBOX1_FLCK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX2 MAILBOX2_FLCK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MCASP1 MCASP1_AHCLKR Func 50 MCASP1_AHCLKR ABE_24M_GFCLK DPLL_DDR
ABE_SYS_CLK SYS_CLK1
FUNC_24M_GFCLK DPLL_PER
SYS_CLK1 OSC0
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 REF_CLKIN0
XREF_CLK1 REF_CLKIN1
XREF_CLK2 REF_CLKIN2
MCASP1_AHCLKX Func 50 MCASP1_AHCLKX ABE_24M_GFCLK DPLL_DDR
ABE_SYS_CLK SYS_CLK1
FUNC_24M_GFCLK DPLL_PER
SYS_CLK1 OSC0
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 REF_CLKIN0
XREF_CLK1 REF_CLKIN1
XREF_CLK2 REF_CLKIN2
MCASP1_FCLK Func 133 MCASP1_AUX_GFCLK L4_ICLK DPLL_CORE
SYS_CLK1 OSC0
MCASP1_ICLK Int 266 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
MCASP2 MCASP2_AHCLKR Func 50 MCASP6_AHCLKR ABE_24M_GFCLK DPLL_DDR
ABE_SYS_CLK SYS_CLK1
FUNC_24M_GFCLK DPLL_PER
SYS_CLK1 OSC0
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 REF_CLKIN0
XREF_CLK1 REF_CLKIN1
XREF_CLK2 REF_CLKIN2
MCASP2_AHCLKX Func 50 MCASP4_AHCLKX ABE_24M_GFCLK DPLL_DDR
ABE_SYS_CLK SYS_CLK1
FUNC_24M_GFCLK DPLL_PER
SYS_CLK1 OSC0
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 REF_CLKIN0
XREF_CLK1 REF_CLKIN1
XREF_CLK2 REF_CLKIN2
MCASP2_FCLK Func 133 MCASP4_AUX_GFCLK L4_ICLK DPLL_CORE
SYS_CLK1 OSC0
MCASP2_ICLK Int 133 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
MCASP3 MCASP3_AHCLKR Func 50 MCASP7_AHCLKR ABE_24M_GFCLK DPLL_DDR
ABE_SYS_CLK SYS_CLK1
FUNC_24M_GFCLK DPLL_PER
SYS_CLK1 OSC0
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 REF_CLKIN0
XREF_CLK1 REF_CLKIN1
XREF_CLK2 REF_CLKIN2
MCASP3_AHCLKX Func 50 MCASP5_AHCLKX ABE_24M_GFCLK DPLL_DDR
ABE_SYS_CLK SYS_CLK1
FUNC_24M_GFCLK DPLL_PER
SYS_CLK1 OSC0
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 REF_CLKIN0
XREF_CLK1 REF_CLKIN1
XREF_CLK2 REF_CLKIN2
MCASP3_FCLK Func 133 MCASP5_AUX_GFCLK L4_ICLK DPLL_CORE
SYS_CLK1 OSC0
MCASP3_ICLK Int 133 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
MCSPI1 SPI1_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
SPI1_FCLK Func 48 PER_48M_GFCLK FUNC_192M_CLK DPLL_PER
MCSPI2 SPI2_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
SPI2_FCLK Func 48 PER_48M_GFCLK FUNC_192M_CLK DPLL_PER
MCSPI3 SPI3_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
SPI3_FCLK Func 48 PER_48M_GFCLK FUNC_192M_CLK DPLL_PER
MCSPI4 SPI4_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
SPI4_FCLK Func 48 PER_48M_GFCLK FUNC_192M_CLK DPLL_PER
MMC1 MMC_CLK_32K Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC0
MMC_FCLK Func 192 MMC4_GFCLK FUNC_192M_CLK DPLL_PER
48 FUNC_48M_FCLK DPLL_PER
MMC_ICLK Int 133 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE
MMU_EDMA MMU_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
OCMC_RAM OCMC_L3_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
OCP_WP_NOC PICLKOCPL3 Int 266 L3INSTR_L3_GICLK CORE_X2_CLK DPLL_CORE
PWMSS1 PWMSS1_GICLK Int & Func 133 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
QSPI QSPI_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
QSPI_FCLK Func 128 QSPI_GFCLK FUNC_128M_CLK DPLL_PER
PER_QSPI_CLK DPLL_PER
RTI1 OCP_CLK_PI Int 133 WKUPAON_GICLK CORE_X2_CLK DPLL_CORE
RTI_CLK_PI Func 13 RTI1_CLK SYS_CLK1/4 OSC0
SYS_CLK2/4 OSC1
FUNC_32K_CLK OSC0
RTI2 OCP_CLK_PI Int 133 WKUPAON_GICLK CORE_X2_CLK DPLL_CORE
RTI_CLK_PI Func 13 RTI2_CLK SYS_CLK1/4 OSC0
SYS_CLK2/4 OSC1
FUNC_32K_CLK OSC0
RTI3 OCP_CLK_PI Int 133 WKUPAON_GICLK CORE_X2_CLK DPLL_CORE
RTI_CLK_PI Func 13 RTI3_CLK SYS_CLK1/4 OSC0
SYS_CLK2/4 OSC1
FUNC_32K_CLK OSC0
RTI4 OCP_CLK_PI Int 133 WKUPAON_GICLK CORE_X2_CLK DPLL_CORE
RTI_CLK_PI Func 13 RTI4_CLK SYS_CLK1/4 OSC0
SYS_CLK2/4 OSC1
FUNC_32K_CLK OSC0
RTI5 OCP_CLK_PI Int 133 WKUPAON_GICLK CORE_X2_CLK DPLL_CORE
RTI_CLK_PI Func 13 RTI5_CLK SYS_CLK1/4 OSC0
SYS_CLK2/4 OSC1
FUNC_32K_CLK OSC0
SD_DAC CLKDAC Func 50 VID_PIX_CLK VID_PIX_CLK DPLL_EVE_VID_DSP
SL2 piclk Int IVA_GCLK IVA_GCLK IVA_GFCLK DPLL_IVA
SPINLOCK SPINLOCK_ICLK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER1 TIMER1_ICLK Int 133 WKUPAON_GICLK SYS_CLK1 OSC0
ABE_LP_CLK DPLL_DDR
TIMER1_FCLK Func 38.4 TIMER1_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 xref_clk0
XREF_CLK1 xref_clk1
ABE_GICLK DPLL_DDR
TIMER2 TIMER2_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER2_FCLK Func 100 TIMER2_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 xref_clk0
XREF_CLK1 xref_clk1
ABE_GICLK DPLL_DDR
TIMER3 TIMER3_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER3_FCLK Func 100 TIMER3_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 xref_clk0
XREF_CLK1 xref_clk1
ABE_GICLK DPLL_DDR
TIMER4 TIMER4_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER4_FCLK Func 100 TIMER4_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 xref_clk0
XREF_CLK1 xref_clk1
ABE_GICLK DPLL_DDR
TIMER5 TIMER5_ICLK Int 133 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER5_FCLK Func 100 TIMER5_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 xref_clk0
XREF_CLK1 xref_clk1
ABE_GICLK DPLL_DDR
CLKOUTMUX0_CLK CLKOUTMUX0
TIMER6 TIMER6_ICLK Int 133 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER6_FCLK Func 100 TIMER6_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 xref_clk0
XREF_CLK1 xref_clk1
ABE_GICLK DPLL_DDR
CLKOUTMUX0_CLK CLKOUTMUX0
TIMER7 TIMER7_ICLK Int 133 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER7_FCLK Func 100 TIMER7_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 xref_clk0
XREF_CLK1 xref_clk1
ABE_GICLK DPLL_DDR
CLKOUTMUX0_CLK CLKOUTMUX0
TIMER8 TIMER8_ICLK Int 133 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER8_FCLK Func 100 TIMER8_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 xref_clk0
XREF_CLK1 xref_clk1
ABE_GICLK DPLL_DDR
CLKOUTMUX0_CLK CLKOUTMUX0
TPCC TPCC_GCLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
TPTC1 TPTC0_GCLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
TPTC2 TPTC1_GCLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
UART1 UART1_FCLK Func 192 UART1_GFCLK FUNC_192M_CLK DPLL_PER
48 FUNC_48M_FCLK DPLL_PER
UART1_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
UART2 UART2_FCLK Func 192 UART2_GFCLK FUNC_192M_CLK DPLL_PER
48 FUNC_48M_FCLK DPLL_PER
UART2_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
UART3 UART3_FCLK Func 192 UART3_GFCLK FUNC_192M_CLK DPLL_PER
48 FUNC_48M_FCLK DPLL_PER
UART3_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
VCP1 VCP1_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
VIP1 PROC_CLK Func 266 VIP1_GCLK L3_ICLK DPLL_CORE
L3_CLK Int CORE_ISS_MAIN_CLK DPLL_CORE
L4_CLK Int 133 VIP1_GCLKDIV2 VIP1_GCLK/2 DPLL_CORE