SPRS975H August   2016  – February 2020 DRA780 , DRA781 , DRA782 , DRA783 , DRA785 , DRA786 , DRA787 , DRA788

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  SD_DAC
      4. 4.3.4  ADC
      5. 4.3.5  Camera Control
      6. 4.3.6  CPI
      7. 4.3.7  CSI2
      8. 4.3.8  EMIF
      9. 4.3.9  GPMC
      10. 4.3.10 Timers
      11. 4.3.11 I2C
      12. 4.3.12 UART
      13. 4.3.13 McSPI
      14. 4.3.14 QSPI
      15. 4.3.15 McASP
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 SDIO Controller
      19. 4.3.19 GPIO
      20. 4.3.20 PWMSS
      21. 4.3.21 ATL
      22. 4.3.22 Test Interfaces
      23. 4.3.23 System and Miscellaneous
        1. 4.3.23.1 Sysboot
        2. 4.3.23.2 Power, Reset and Clock Management (PRCM)
        3. 4.3.23.3 Enhanced Direct Memory Access (EDMA)
        4. 4.3.23.4 Interrupt Controllers (INTC)
      24. 4.3.24 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS Analog OSC Buffers DC Electrical Characteristics
      6. Table 5-11 Dual Voltage LVCMOS DC Electrical Characteristics
      7. Table 5-12 Analog-to-Digital ADC Subsystem Electrical Specifications
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Timing Requirements and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
        1. 5.9.1.1 Parameter Information
          1. 5.9.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.9.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.9.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.9.2 Interface Clock Specifications
        1. 5.9.2.1 Interface Clock Terminology
        2. 5.9.2.2 Interface Clock Frequency
      3. 5.9.3 Power Supply Sequences
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 OSC0 External Crystal
          2. 5.9.4.1.2 OSC0 Input Clock
          3. 5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.9.4.1.3.1 OSC1 External Crystal
            2. 5.9.4.1.3.2 OSC1 Input Clock
          4. 5.9.4.1.4 RC On-die Oscillator Clock
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 DPLLs, DLLs
          1. 5.9.4.3.1 DPLL Characteristics
          2. 5.9.4.3.2 DLL Characteristics
            1. 5.9.4.3.2.1 DPLL and DLL Noise Isolation
      5. 5.9.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.9.6 Peripherals
        1. 5.9.6.1  Timing Test Conditions
        2. 5.9.6.2  VIP
        3. 5.9.6.3  DSS
        4. 5.9.6.4  EMIF
        5. 5.9.6.5  GPMC
          1. 5.9.6.5.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.9.6.5.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.9.6.5.3 GPMC/NAND Flash Interface Asynchronous Timing
        6. 5.9.6.6  GP Timers
          1. 5.9.6.6.1 GP Timer Features
        7. 5.9.6.7  I2C
          1. Table 5-39 Timing Requirements for I2C Input Timings
          2. Table 5-40 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        8. 5.9.6.8  UART
          1. Table 5-41 Timing Requirements for UART
          2. Table 5-42 Switching Characteristics Over Recommended Operating Conditions for UART
        9. 5.9.6.9  McSPI
        10. 5.9.6.10 QSPI
        11. 5.9.6.11 McASP
          1. Table 5-50 Timing Requirements for McASP1
          2. Table 5-51 Timing Requirements for McASP2
          3. Table 5-52 Timing Requirements for McASP3
          4. Table 5-53 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-54 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-55 Switching Characteristics Over Recommended Operating Conditions for McASP3
        12. 5.9.6.12 DCAN and MCAN
          1. 5.9.6.12.1 DCAN
          2. 5.9.6.12.2 MCAN
          3. Table 5-58 Timing Requirements for CAN Receive
          4. Table 5-59 Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
        13. 5.9.6.13 GMAC_SW
          1. 5.9.6.13.1 GMAC MDIO Interface Timings
          2. 5.9.6.13.2 GMAC RGMII Timings
            1. Table 5-63 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-64 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-65 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-66 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        14. 5.9.6.14 SDIO Controller
          1. 5.9.6.14.1 MMC, SD Default Speed
          2. 5.9.6.14.2 MMC, SD High Speed
          3. 5.9.6.14.3 MMC, SD and SDIO SDR12 Mode
          4. 5.9.6.14.4 MMC, SD SDR25 Mode
        15. 5.9.6.15 GPIO
        16. 5.9.6.16 ATL
          1. 5.9.6.16.1 ATL Electrical Data/Timing
            1. Table 5-77 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
      7. 5.9.7 Emulation and Debug Subsystem
        1. 5.9.7.1 JTAG Electrical Data/Timing
          1. Table 5-78 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 5-79 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 5-80 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 5-81 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.9.7.2 Trace Port Interface Unit (TPIU)
          1. 5.9.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 DSP Subsystem
      2. 6.2.2 IPU
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 EVE
    4. 6.4 Other Subsystems
      1. 6.4.1 Memory Subsystem
        1. 6.4.1.1 EMIF
        2. 6.4.1.2 GPMC
        3. 6.4.1.3 ELM
        4. 6.4.1.4 OCMC
      2. 6.4.2 Interprocessor Communication
        1. 6.4.2.1 Mailbox
        2. 6.4.2.2 Spinlock
      3. 6.4.3 Interrupt Controller
      4. 6.4.4 EDMA
      5. 6.4.5 Peripherals
        1. 6.4.5.1  VIP
        2. 6.4.5.2  DSS
        3. 6.4.5.3  ATL
        4. 6.4.5.4  ADC
        5. 6.4.5.5  Timers
          1. 6.4.5.5.1 General-Purpose Timers
          2. 6.4.5.5.2 32-kHz Synchronized Timer (COUNTER_32K)
        6. 6.4.5.6  I2C
        7. 6.4.5.7  UART
        8. 6.4.5.8  McSPI
        9. 6.4.5.9  QSPI
        10. 6.4.5.10 McASP
        11. 6.4.5.11 DCAN
        12. 6.4.5.12 MCAN
        13. 6.4.5.13 GMAC_SW
        14. 6.4.5.14 SDIO
        15. 6.4.5.15 GPIO
        16. 6.4.5.16 ePWM
        17. 6.4.5.17 eCAP
        18. 6.4.5.18 eQEP
      6. 6.4.6 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing-Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing-Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_dspeve Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
        1. 7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR2 Board Design and Layout Guidelines
      1. 7.7.1 DDR2 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
    8. 7.8 DDR3 Board Design and Layout Guidelines
      1. 7.8.1 DDR3 General Board Layout Guidelines
      2. 7.8.2 DDR3 Board Design and Layout Guidelines
        1. 7.8.2.1  Board Designs
        2. 7.8.2.2  DDR3 Device Combinations
        3. 7.8.2.3  DDR3 Interface Schematic
          1. 7.8.2.3.1 32-Bit DDR3 Interface
          2. 7.8.2.3.2 16-Bit DDR3 Interface
        4. 7.8.2.4  Compatible JEDEC DDR3 Devices
        5. 7.8.2.5  PCB Stackup
        6. 7.8.2.6  Placement
        7. 7.8.2.7  DDR3 Keepout Region
        8. 7.8.2.8  Bulk Bypass Capacitors
        9. 7.8.2.9  High Speed Bypass Capacitors
          1. 7.8.2.9.1 Return Current Bypass Capacitors
        10. 7.8.2.10 Net Classes
        11. 7.8.2.11 DDR3 Signal Termination
        12. 7.8.2.12 VTT
        13. 7.8.2.13 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.8.2.13.1 Three DDR3 Devices
            1. 7.8.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 7.8.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 7.8.2.13.2 Two DDR3 Devices
            1. 7.8.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.8.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.8.2.13.3 One DDR3 Device
            1. 7.8.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.8.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        14. 7.8.2.14 Data Topologies and Routing Definition
          1. 7.8.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.8.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 7.8.2.15 Routing Specification
          1. 7.8.2.15.1 CK and ADDR_CTRL Routing Specification
          2. 7.8.2.15.2 DQS and DQ Routing Specification
    9. 7.9 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABF|367
サーマルパッド・メカニカル・データ
発注情報

4.3.1 VIP

NOTE

For more information, see the Video Input Port (VIP) section in the device TRM.

CAUTION

The IO timings provided in Section 5.9, Timing Requirements and Switching Characteristics are only valid for VIN1 and VIN2 if signals within a single IOSET are used. The IOSETs are defined in Table 5-28 and Table 5-29.

Table 4-2 VIP Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Video Input 1
vin1a_clk0 Video Input 1 Port A Clock input. Input clock for 8-bit 16-bit or 24-bit Port A video capture. Input data is sampled on the CLK0 edge. I F22
vin1a_d0 Video Input 1 Port A Data input I G18
vin1a_d1 Video Input 1 Port A Data input I G21
vin1a_d2 Video Input 1 Port A Data input I G22
vin1a_d3 Video Input 1 Port A Data input I H18
vin1a_d4 Video Input 1 Port A Data input I H20
vin1a_d5 Video Input 1 Port A Data input I H19
vin1a_d6 Video Input 1 Port A Data input I H22
vin1a_d7 Video Input 1 Port A Data input I H21
vin1a_d8 Video Input 1 Port A Data input I J17
vin1a_d9 Video Input 1 Port A Data input I K22
vin1a_d10 Video Input 1 Port A Data input I K21
vin1a_d11 Video Input 1 Port A Data input I K18
vin1a_d12 Video Input 1 Port A Data input I AB17,K17
vin1a_d13 Video Input 1 Port A Data input I K19,U17
vin1a_d14 Video Input 1 Port A Data input I K20,W17
vin1a_d15 Video Input 1 Port A Data input I AA17,L21
vin1a_de0 Video Input 1 Port A Field ID input I F19,F21
vin1a_fld0 Video Input 1 Port A Field ID input I F20
vin1a_hsync0 Video Input 1 Port A Horizontal Sync input I F19
vin1a_vsync0 Video Input 1 Port A Vertical Sync input I G19
vin1b_clk1 Video Input 1 Port B Clock input I F21
vin1b_d0 Video Input 1 Port B Data input I J17
vin1b_d1 Video Input 1 Port B Data input I K22
vin1b_d2 Video Input 1 Port B Data input I K21
vin1b_d3 Video Input 1 Port B Data input I K18
vin1b_d4 Video Input 1 Port B Data input I K17
vin1b_d5 Video Input 1 Port B Data input I K19
vin1b_d6 Video Input 1 Port B Data input I K20
vin1b_d7 Video Input 1 Port B Data input I L21
vin1b_de1 Video Input 1 Port B Field ID input I W7
vin1b_hsync1 Video Input 1 Port B Horizontal Sync input I W7
vin1b_vsync1 Video Input 1 Port B Vertical Sync input I W6
Video Input 2
vin2a_clk0 Video Input 2 Port A Clock input I AB17,L22,W15
vin2a_d0 Video Input 2 Port A Data input I AA14
vin2a_d1 Video Input 2 Port A Data input I AB14
vin2a_d2 Video Input 2 Port A Data input I U13
vin2a_d3 Video Input 2 Port A Data input I V13
vin2a_d4 Video Input 2 Port A Data input I Y13
vin2a_d5 Video Input 2 Port A Data input I W13
vin2a_d6 Video Input 2 Port A Data input I U11
vin2a_d7 Video Input 2 Port A Data input I V11
vin2a_d8 Video Input 2 Port A Data input I U9
vin2a_d9 Video Input 2 Port A Data input I W11
vin2a_d10 Video Input 2 Port A Data input I V9
vin2a_d11 Video Input 2 Port A Data input I W9
vin2a_d12 Video Input 2 Port A Data input I U8
vin2a_d13 Video Input 2 Port A Data input I W8
vin2a_d14 Video Input 2 Port A Data input I U7
vin2a_d15 Video Input 2 Port A Data input I V7
vin2a_de0 Video Input 2 Port A Field ID input I AA15,AA17,M17,W7
vin2a_fld0 Video Input 2 Port A Field ID input I AB15,M18,U16
vin2a_hsync0 Video Input 2 Port A Horizontal Sync input I F14,F15,W7
vin2a_vsync0 Video Input 2 Port A Vertical Sync input I C14,F16,W6
vin2b_clk1 Video Input 2 Port B Clock input I F20
vin2b_d0 Video Input 2 Port B Data input I U9
vin2b_d1 Video Input 2 Port B Data input I W11
vin2b_d2 Video Input 2 Port B Data input I V9
vin2b_d3 Video Input 2 Port B Data input I W9
vin2b_d4 Video Input 2 Port B Data input I U8
vin2b_d5 Video Input 2 Port B Data input I W8
vin2b_d6 Video Input 2 Port B Data input I U7
vin2b_d7 Video Input 2 Port B Data input I V7
vin2b_de1 Video Input 2 Port B Field ID input I M17
vin2b_hsync1 Video Input 2 Port B Horizontal Sync input I M17
vin2b_vsync1 Video Input 2 Port B Vertical Sync input I M18