JAJSFR8E August   2016  – May 2019 DRA790 , DRA791 , DRA793 , DRA797

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hour (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IPU
    6. 6.6  PRU-ICSS
    7. 6.7  Memory Subsystem
      1. 6.7.1 EMIF
      2. 6.7.2 GPMC
      3. 6.7.3 ELM
      4. 6.7.4 OCMC
    8. 6.8  Interprocessor Communication
      1. 6.8.1 MailBox
      2. 6.8.2 Spinlock
    9. 6.9  Interrupt Controller
    10. 6.10 EDMA
    11. 6.11 Peripherals
      1. 6.11.1  VIP
      2. 6.11.2  DSS
      3. 6.11.3  Timers
        1. 6.11.3.1 General-Purpose Timers
        2. 6.11.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.11.3.3 Watchdog Timer
      4. 6.11.4  I2C
      5. 6.11.5  UART
        1. 6.11.5.1 UART Features
        2. 6.11.5.2 IrDA Features
        3. 6.11.5.3 CIR Features
      6. 6.11.6  McSPI
      7. 6.11.7  QSPI
      8. 6.11.8  McASP
      9. 6.11.9  USB
      10. 6.11.10 PCIe
      11. 6.11.11 DCAN
      12. 6.11.12 GMAC_SW
      13. 6.11.13 eMMC/SD/SDIO
      14. 6.11.14 GPIO
      15. 6.11.15 ePWM
      16. 6.11.16 eCAP
      17. 6.11.17 eQEP
    12. 6.12 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • CBD|538
サーマルパッド・メカニカル・データ
発注情報

Table 5-73 Timing Requirements for McASP3/4/5/6/7/8(1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
1 tc(AHCLKX) Cycle time, AHCLKX 20 ns
2 tw(AHCLKX) Pulse duration, AHCLKX high or low 0.35P (2) ns
3 tc(ACLKRX) Cycle time, ACLKR/X 20 ns
4 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5R - 3 (3) ns
5 tsu(AFSRX-ACLK) Setup time, AFSR/X input valid before ACLKR/X ACLKR/X int 19.7 ns
ACLKR/X ext in
ACLKR/X ext out		 5.6 ns
6 th(ACLK-AFSRX) Hold time, AFSR/X input valid after ACLKR/X ACLKR/X int -1.1 ns
ACLKR/X ext in
ACLKR/X ext out		 2.5 ns
tsu(AXR-ACLK) Setup time, AXR input valid before ACLKX ACLKX int (ASYNC=0) 20.3 ns
ACLKR/X ext in
ACLKR/X ext out		 5.1 ns
8 th(ACLK-AXR) Hold time, AXR input valid after ACLKX ACLKX int (ASYNC=0) -0.8 ns
ACLKR/X ext in
ACLKR/X ext out		 2.5 ns
  1. ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)
    ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
    ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
    ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
    ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
    ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
  2. P = AHCLKX period in ns.
  3. R = ACLKR/X period in ns.
DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_McASP_01.gif
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).
Figure 5-57 McASP Input Timing

CAUTION

The I/O Timings provided in this section are valid only for some McASP usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 5-74, Table 5-75, Table 5-76 and Figure 5-58 present Switching Characteristics Over Recommended Operating Conditions for McASP1 to McASP8.

Table 5-74 Switching Characteristics Over Recommended Operating Conditions for McASP1(1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
9 tc(AHCLKX) Cycle time, AHCLKX 20 ns
10 tw(AHCLKX) Pulse duration, AHCLKX high or low 0.5P - 2.5 (2) ns
11 tc(ACLKRX) Cycle time, ACLKR/X 20 ns
12 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5P - 2.5 (3) ns
13 td(ACLK-AFSXR) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int -0.9 6 ns
ACLKR/X ext in
ACLKR/X ext out		 2 23.1 ns
14 td(ACLK-AXR) Delay time, ACLKR/X transmit edge to AXR output valid ACLKR/X int -1.4 6 ns
ACLKR/X ext in
ACLKR/X ext out		 2 24.2 ns

Table 5-75 Switching Characteristics Over Recommended Operating Conditions for McASP2 (1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
9 tc(AHCLKX) Cycle time, AHCLKX 20 ns
10 tw(AHCLKX) Pulse duration, AHCLKX high or low 0.5P - 2.5 (2) ns
11 tc(ACLKX) Cycle time, ACLKX 20 ns
12 tw(ACLKX) Pulse duration, ACLKX high or low 0.5P - 2.5 (3) ns
13 td(ACLK-AFSX) Delay time, ACLKX transmit edge to AFSX output valid ACLKX int -1 6 ns
ACLKX ext in
ACLKX ext out		 2 23.2 ns
14 td(ACLK-AXR) Delay time, ACLKX transmit edge to AXR output valid ACLKX int -1.3 6 ns
ACLKX ext in
ACLKX ext out		 2 23.7 ns

Table 5-76 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8(1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
9 tc(AHCLKX) Cycle time, AHCLKX 20 ns
10 tw(AHCLKX) Pulse duration, AHCLKX high or low 0.5P - 2.5 (2) ns
11 tc(ACLKRX) Cycle time, ACLKR/X 20 ns
12 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5P - 2.5 (3) ns
13 td(ACLK-AFSXR) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int -0.5 6 ns
ACLKR/X ext in
ACLKR/X ext out		 1.9 24.5 ns
14 td(ACLK-AXR) Delay time, ACLKR/X transmit edge to AXR output valid ACLKR/X int -1.4 7.1 ns
ACLKR/X ext in
ACLKR/X ext out		 1.1 24.2 ns
DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_McASP_02.gif
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).
Figure 5-58 McASP Output TimingAB

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-32 and described in Device TRM, Control Module Chapter.

Table 5-77 through Table 5-84 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see Figure 5-59 through Figure 5-66).

Table 5-77 Virtual Mode Case Details for McASP1

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-59
AXR(Inputs)/CLKR/FSR MCASP1_VIRTUAL2_ASYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP1_VIRTUAL2_ASYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL2_ASYNC_RX See Figure 5-61
AXR(Inputs)/CLKR/FSR Default (No Virtual Mode)
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL2_ASYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR Default (No Virtual Mode)
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-63
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL1_SYNC_RX See Figure 5-64
AXR(Inputs)/CLKX/FSX MCASP1_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL1_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP1_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-66
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-78 Virtual Mode Case Details for McASP2

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-63
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL3_SYNC_RX See Figure 5-64
AXR(Inputs)/CLKX/FSX MCASP2_VIRTUAL3_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL3_SYNC_RX(1) See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP2_VIRTUAL3_SYNC_RX(1)
AXR(Inputs)/CLKX/FSX MCASP2_VIRTUAL1_SYNC_RX_80M(2)
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-66
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
  1. Used up to 50MHz. Should also be used in a CI-FI- mixed case where AXR operate as both inputs and outputs (that is, AXR are bidirectional).
  2. Used in 80MHz input only mode when AXR, CLKX and FSX are all inputs.

Table 5-79 Virtual Mode Case Details for McASP3

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-59
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-63
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 5-64
AXR(Inputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-66
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-80 Virtual Mode Case Details for McASP4

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-59
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-63
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 5-64
AXR(Inputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-66
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-81 Virtual Mode Case Details for McASP5

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-59
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-63
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 5-64
AXR(Inputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-66
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-82 Virtual Mode Case Details for McASP6

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-59
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-63
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 5-64
AXR(Inputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-66
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-83 Virtual Mode Case Details for McASP7

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-59
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-63
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 5-64
AXR(Inputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-66
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-84 Virtual Mode Case Details for McASP8

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-59
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-63
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 5-64
AXR(Inputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-66
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
DRA790 DRA791 DRA793 DRA797 SPRS906_MCASP_uc_01.gifFigure 5-59 McASP1-8 COIFOI – ASYNC Mode
DRA790 DRA791 DRA793 DRA797 SPRS906_MCASP_uc_02.gifFigure 5-60 McASP1-8 COIFIO – ASYNC Mode
DRA790 DRA791 DRA793 DRA797 SPRS906_MCASP_uc_03.gifFigure 5-61 McASP1-8 CIOFIO – ASYNC Mode
DRA790 DRA791 DRA793 DRA797 SPRS906_MCASP_uc_04.gifFigure 5-62 McASP1-8 CIOFOI – ASYNC Mode
DRA790 DRA791 DRA793 DRA797 SPRS906_MCASP_uc_05.gifFigure 5-63 McASP1-8 CO-FO- – SYNC Mode
DRA790 DRA791 DRA793 DRA797 SPRS906_MCASP_uc_06.gifFigure 5-64 McASP1-8 CI-FO- – SYNC Mode
DRA790 DRA791 DRA793 DRA797 SPRS906_MCASP_uc_07.gifFigure 5-65 McASP1-8 CI-FI- – SYNC Mode
DRA790 DRA791 DRA793 DRA797 SPRS906_MCASP_uc_08.gifFigure 5-66 McASP1-8 CO-FI- – SYNC Mode

Virtual IO Timings Modes must be used to ensure some IO timings for McASP1. See Table 5-29Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-85Virtual Functions Mapping for McASP1 for a definition of the Virtual modes.

Table 5-85 presents the values for DELAYMODE bitfield.

Table 5-85 Virtual Functions Mapping for McASP1

BALL BALL NAME Delay Mode Value MUXMODE
MCASP1_VIRTUAL1_SYNC_RX MCASP1_VIRTUAL2_ASYNC_RX 0 1 2
C16 mcasp1_aclkx 15 14 mcasp1_aclkx
H21 gpio6_14 14 13 mcasp1_axr8
E17 mcasp1_axr13 15 14 mcasp1_axr13
A15 mcasp1_axr4 14 13 mcasp1_axr4
H24 xref_clk2 14 13 mcasp1_axr6
B17 mcasp1_axr9 15 14 mcasp1_axr9
A16 mcasp1_axr7 14 13 mcasp1_axr7
A19 mcasp1_axr12 15 14 mcasp1_axr12
K23 gpio6_16 14 13 mcasp1_axr10
K22 gpio6_15 14 13 mcasp1_axr9
H25 xref_clk3 14 13 mcasp1_axr7
A17 mcasp1_axr6 14 13 mcasp1_axr6
B16 mcasp1_axr10 15 14 mcasp1_axr10
D17 mcasp1_fsr N/A 14 mcasp1_fsr
A18 mcasp1_axr8 15 14 mcasp1_axr8
B18 mcasp1_axr11 15 14 mcasp1_axr11
C14 mcasp1_axr2 14 13 mcasp1_axr2
C17 mcasp1_fsx 15 14 mcasp1_fsx
E16 mcasp1_axr14 15 14 mcasp1_axr14
F16 mcasp1_axr15 15 14 mcasp1_axr15
B14 mcasp1_axr1 15 14 mcasp1_axr1
D16 mcasp1_aclkr N/A 14 mcasp1_aclkr
A14 mcasp1_axr5 14 13 mcasp1_axr5
J24 xref_clk1 15 14 mcasp1_axr5
D14 mcasp1_axr0 15 14 mcasp1_axr0
B15 mcasp1_axr3 14 13 mcasp1_axr3
J25 xref_clk0 15 14 mcasp1_axr4

Virtual IO Timings Modes must be used to ensure some IO timings for McASP2. See Table 5-29Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-86Virtual Functions Mapping for McASP2 for a definition of the Virtual modes.

Table 5-86 presents the values for DELAYMODE bitfield.

Table 5-86 Virtual Functions Mapping for McASP2

BALL BALL NAME Delay Mode Value MUXMODE
MCASP2_VIRTUAL1
_SYNC_RX_80M		 MCASP2_VIRTUAL2
_ASYNC_RX 		MCASP2_VIRTUAL3
_SYNC_RX		 MCASP2_VIRTUAL4
_ASYNC_RX_80M		 0 1 2
B22 mcasp3_axr0 15 14 10 9 mcasp2_axr14
D20 mcasp2_axr6 14 13 12 11 mcasp2_axr6
C19 mcasp2_axr5 14 13 12 11 mcasp2_axr5
D19 mcasp2_fsx 15 14 10 9 mcasp2_fsx
H24 xref_clk2 12 11 10 9 mcasp2_axr10
B21 mcasp2_axr3 15 14 10 9 mcasp2_axr3
A22 mcasp3_aclkx 15 14 10 9 mcasp2_axr12
E19 mcasp2_aclkx 15 14 10 9 mcasp2_aclkx
C20 mcasp2_axr7 14 13 12 11 mcasp2_axr7
H25 xref_clk3 12 11 10 9 mcasp2_axr11
B23 mcasp3_axr1 15 14 10 8 mcasp2_axr15
A23 mcasp3_fsx 15 14 10 9 mcasp2_axr13
A21 mcasp2_axr2 15 14 10 9 mcasp2_axr2
B20 mcasp2_axr4 14 13 12 11 mcasp2_axr4
J24 xref_clk1 10 9 8 6 mcasp2_axr9
B19 mcasp2_axr1 14 13 12 11 mcasp2_axr1
A20 mcasp2_axr0 14 13 12 11 mcasp2_axr0
J25 xref_clk0 10 9 8 6 mcasp2_axr8

Virtual IO Timings Modes must be used to ensure some IO timings for McASP3/4/5/6/7/8. See Table 5-29Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-87Virtual Functions Mapping for McASP3/4/5/6/7/8 for a definition of the Virtual modes.

Table 5-87 presents the values for DELAYMODE bitfield.

Table 5-87 Virtual Functions Mapping for McASP3/4/5/6/7/8

BALL BALL NAME Delay Mode Value MUXMODE
0 1 2
MCASP3_VIRTUAL2_SYNC_RX
B21 mcasp2_axr3 8 mcasp3_axr3
A22 mcasp3_aclkx 8 mcasp3_aclkx mcasp3_aclkr
B22 mcasp3_axr0 8 mcasp3_axr0
B23 mcasp3_axr1 6 mcasp3_axr1
A23 mcasp3_fsx 8 mcasp3_fsx mcasp3_fsr
A21 mcasp2_axr2 8 mcasp3_axr2
MCASP4_VIRTUAL1_SYNC_RX
B25 mcasp4_fsx 14 mcasp4_fsx mcasp4_fsr
C23 mcasp4_aclkx 14 mcasp4_aclkx mcasp4_aclkr
A24 mcasp4_axr0 14 mcasp4_axr0
D23 mcasp4_axr1 14 mcasp4_axr1
A14 mcasp1_axr5 12 mcasp4_axr3
A15 mcasp1_axr4 12 mcasp4_axr2
MCASP5_VIRTUAL1_SYNC_RX
AC3 mcasp5_aclkx 14 mcasp5_aclkx mcasp5_aclkr
U6 mcasp5_fsx 14 mcasp5_fsx mcasp5_fsr
AC4 mcasp5_axr1 14 mcasp5_axr1
A17 mcasp1_axr6 12 mcasp5_axr2
AA5 mcasp5_axr0 14 mcasp5_axr0
A16 mcasp1_axr7 12 mcasp5_axr3
MCASP6_VIRTUAL1_SYNC_RX
C14 mcasp1_axr2 12 mcasp6_axr2
B15 mcasp1_axr3 12 mcasp6_axr3
B16 mcasp1_axr10 10 mcasp6_aclkx mcasp6_aclkr
B17 mcasp1_axr9 10 mcasp6_axr1
A18 mcasp1_axr8 10 mcasp6_axr0
B18 mcasp1_axr11 10 mcasp6_fsx mcasp6_fsr
MCASP7_VIRTUAL2_SYNC_RX
A19 mcasp1_axr12 10 mcasp7_axr0
F16 mcasp1_axr15 10 mcasp7_fsx mcasp7_fsr
E16 mcasp1_axr14 10 mcasp7_aclkx mcasp7_aclkr
E17 mcasp1_axr13 10 mcasp7_axr1
D16 mcasp1_aclkr 13 mcasp7_axr2
D17 mcasp1_fsr 13 mcasp7_axr3
MCASP8_VIRTUAL1_SYNC_RX
B20 mcasp2_axr4 10 mcasp8_axr0
C20 mcasp2_axr7 10 mcasp8_fsx mcasp8_fsr
D20 mcasp2_axr6 10 mcasp8_aclkx mcasp8_aclkr
C19 mcasp2_axr5 10 mcasp8_axr1