JAJSII9 データシート

JAJSII9E april 2020 – june 2023 DRA821U , DRA821U-Q1

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ALM|433

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7.9.2.2 Combined MCU and Main Domains Power- Up Sequencing

Figure 7-9 describes the primary power-up sequencing when similar MCU and Main voltage domains are combined into common power rails. Combining MCU and Main voltage domains makes an SoC’s MCU and Main processor sub-systems operational dependent on common power rails. The main reason an SoC’s PDN design may want to group MCU and Main voltage domains is simplify the PDN by reducing total number of power rails and sources. This simplified PDN would be used in systems that do not desire independent MCU and Main processor sub-system operations.

A. Terminology:

Primary = Essential power up sequence of all voltage domains to full active state.
V_{OPR MIN} = Minimum operational voltage level that ensures functionality as specified in , Recommended Operating Conditions.
Ramp Up = Voltage supply transition time from off condition to V_{OPR MIN}.
Domain_“n” = multiple instances of similar voltage domains (that is, dual voltage IO domains, VDDSHVn = VDDSHV0, VDDSHV1, VDDSHV2 … VDDSHV6)
Domain_“xxx” = different signal type/protocol domains using same voltage supply type and level (that is, VDDA_1P8_xx = VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)

Time stamps:
Markers showing approximate elapsed times that are dependent upon PDN feature set, component selection and power mapping. Values shown are typical for PDNs combining MCU and Main voltage domains but could vary based upon PDN design.
Time Stamp definitions and (typical values for reference only):
T0 – All 3.3-V voltages start supply ramp-up to V_{OPR MIN}. (0 ms)
T1 – All 1.8-V voltages start supply ramp-up to V_{OPR
MIN}. (0.5 ms)
T2 – All core voltages start supply ramp-up to V_{OPR MIN}. (1.0 ms)
T3 – All RAM array voltages start supply ramp-up to V_{OPR
MIN}. (1.5 ms)
T4 – OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (11 ms)

B. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.

C. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.

D. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8 V) power rail is required for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed 3.3-V operation is acceptable, then domain can be grouped with digital IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO 1.8-V power rail.

E. VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3-V digital IO power rail either directly or through a supply filter.

F. VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy> domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.

G. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-line supply filter is allowed.

H. VDDA_0P8_<dll/pll> are 0.8 V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals.

I. VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or 0.85-V RAM array (VDDAR_xxx) domains.

J. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch MCU_BOOTMODEn (referenced to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings into registers during power-up sequence.

K. Minimum elapsed time from crystal oscillator circuitry being energized (VDDA_OSC1 at T1) until stable clock frequency is reached depends upon on crystal oscillator, capacitor parameters and PCB parasitic values. A conservative 10- ms elapsed time defined by (T4 – T1) time stamps is shown. This could be reduced depending upon customer’s clock circuit (that is, crystal oscillator or clock generator) and PCB designs.

Figure 7-3 Combined MCU and Main Domains, Primary Power-Up Sequence